{"title":"微处理器外围系统的事件控制和编程","authors":"Rune André Bjørnerud, Morten W. Lund, K. Svarstad","doi":"10.1109/NORCHP.2009.5397807","DOIUrl":null,"url":null,"abstract":"Standard microcontrollers waste a significant amount of CPU cycles in order to handle I/O and peripheral resources. To handle communication between on-chip peripherals without interference from CPU, DMA or interrupt resources, the Atmel® AVR® XMEGA¿ 1 microcontroller introduces a peripheral resource known as the Event System. The Event System currently implemented on the AVR XMEGA offers limited resources for logical event computation, and can be used as a basic routing facility for I/O and peripipheral signals. The present work proposes a novel extension to the Event System. In order to enhance routing flexibility a programmable asynchronous interconnect topology with pipelined switches has been designed, leading to increased computational power through the use of asynchronous LUTs to handle logical event computations.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Event control and programming for microprocessor peripheral systems\",\"authors\":\"Rune André Bjørnerud, Morten W. Lund, K. Svarstad\",\"doi\":\"10.1109/NORCHP.2009.5397807\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Standard microcontrollers waste a significant amount of CPU cycles in order to handle I/O and peripheral resources. To handle communication between on-chip peripherals without interference from CPU, DMA or interrupt resources, the Atmel® AVR® XMEGA¿ 1 microcontroller introduces a peripheral resource known as the Event System. The Event System currently implemented on the AVR XMEGA offers limited resources for logical event computation, and can be used as a basic routing facility for I/O and peripipheral signals. The present work proposes a novel extension to the Event System. In order to enhance routing flexibility a programmable asynchronous interconnect topology with pipelined switches has been designed, leading to increased computational power through the use of asynchronous LUTs to handle logical event computations.\",\"PeriodicalId\":308859,\"journal\":{\"name\":\"2009 NORCHIP\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 NORCHIP\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2009.5397807\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2009.5397807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Event control and programming for microprocessor peripheral systems
Standard microcontrollers waste a significant amount of CPU cycles in order to handle I/O and peripheral resources. To handle communication between on-chip peripherals without interference from CPU, DMA or interrupt resources, the Atmel® AVR® XMEGA¿ 1 microcontroller introduces a peripheral resource known as the Event System. The Event System currently implemented on the AVR XMEGA offers limited resources for logical event computation, and can be used as a basic routing facility for I/O and peripipheral signals. The present work proposes a novel extension to the Event System. In order to enhance routing flexibility a programmable asynchronous interconnect topology with pipelined switches has been designed, leading to increased computational power through the use of asynchronous LUTs to handle logical event computations.