On-chip offset generator for A/D converter INL testing without an accurate test stimulus

Abstract

Means of testing the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus have recently been proposed. These methods are based on a constant DC offset between two low-quality test signals. We describe here an on-chip offset generator and analyse its limitations. Experimental tests show that it can be used to test the INL of 12-b ADCs.