2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397827
J. Ollikainen, M. Kaltiokallio, K. Stadius, V. Saari, J. Ryynanen
{"title":"A wideband interference tolerant RF receiver for cognitive radio sensor unit","authors":"J. Ollikainen, M. Kaltiokallio, K. Stadius, V. Saari, J. Ryynanen","doi":"10.1109/NORCHP.2009.5397827","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397827","url":null,"abstract":"A wideband receiver for cognitive radio spectrum sensing unit is presented. The circuit consists of a high linearity low noise amplifier, passive mixer, and baseband buffer. IQ signals for the LO are generated using a divide-by-two circuit. Low noise amplifier includes common-gate common-source combination for simultaneous interference suppression and noise canceling. The receiver operates in the LTE bands at 0.7 - 2.6 GHz, with typical performance of 32 dB gain, 5 dB noise figure, and IIP3 linearity between 5 dBm and -1 dBm in the LTE bandwidth. The circuit is designed for 65-nm CMOS technology.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":" 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113950720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397824
M. Atef, W. Gaberl, R. Swoboda, H. Zimmermann
{"title":"An integrated optical receiver for multilevel data communication over plastic optical fiber","authors":"M. Atef, W. Gaberl, R. Swoboda, H. Zimmermann","doi":"10.1109/NORCHP.2009.5397824","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397824","url":null,"abstract":"A BiCMOS integrated optical receiver with high sensitivity and linearity is presented. An automatic gain control transimpedance amplifier and linear post amplifiers are used to maintain a high linearity with multilevel modulation. Using multilevel signaling and large-diameter integrated photodiodes make the presented optical receiver suitable for small-bandwidth high-attenuation large-core PMMA step index plastic optical fiber. A measured sensitivity of −31dBm (BER=10−9) at 250Mb/s is presented for a binary signal. A data rate of 500Mb/s and a sensitivity of −25dBm (BER=10−9) are achieved with four-level pulse amplitude modulation (4-PAM). An error-free transmission over 40m PMMA step index plastic optical fiber was achieved at 500Mb/s using 4-PAM signaling with the presented multilevel optical receiver.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123851426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397811
G. Valters, P. Misans
{"title":"FPGA implementation of Elementary Generalized Unitary Rotation","authors":"G. Valters, P. Misans","doi":"10.1109/NORCHP.2009.5397811","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397811","url":null,"abstract":"This paper describes the first trial of implementation of generalized unitary Jacobi-like rotation (device is called as EGURM-rotator, further as rotator) into Altera's FPGA. Basics and examples of the generalized rotation matrix are given. Algorithms for implementation of parametrical rotator are provided. Architectures of rotator are briefly described. Different rotator versions are compared by the number of operations. Rotator with serial input is recommended for the further development and mostly applications because of twice reduced number of adders and multipliers. Versions of rotator devices differ by sine/cosine former blocks implemented using CORDIC and RAM table. A CORDIC former ensures better accuracy in comparison to the table former but slows the speed of rotator. The number of logic cells are given for different wordlengths.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116243401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397843
A. Domdey, K. M. Hafkemeyer, D. Schroeder, W. Krautschneider
{"title":"Reliability analysis of gate dielectrics by applying array test structures and automated test systems","authors":"A. Domdey, K. M. Hafkemeyer, D. Schroeder, W. Krautschneider","doi":"10.1109/NORCHP.2009.5397843","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397843","url":null,"abstract":"In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to stress up to 4k DUTs under same conditions. Several array test structures with different perimeters as well as areas integrated on one chip are available. Low-cost automated test systems allow for gate voltage stress experiments on a large scale with numerous array test structures in parallel. Experimental results are shown.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397802
Cheng Tao, P. Teemu, T. Esa, H. Tenhunen, T. Tikka, J. Ryynanen
{"title":"Impact of circuit non-idealities on wireless interconnect based on OOK modulated RF transceiver","authors":"Cheng Tao, P. Teemu, T. Esa, H. Tenhunen, T. Tikka, J. Ryynanen","doi":"10.1109/NORCHP.2009.5397802","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397802","url":null,"abstract":"In this work, a system model for RF wireless interconnect has been proposed based on digital on-off keying (OOK) modulated RF transceiver with 2Gb/s transmission rate and 40GHz carrier frequency. To evaluate performance of wireless interconnect, the impact of critical non-idealities caused by circuit blocks has been analyzed and simulated in Matlab® Simulink® environment. A set of rough circuit specifications and BER performances of such system are obtained, through which key points during actual circuit design has come into view. The result of this work has verified the potential feasibility and reliability, and pointed out possible circuit design stresses for wireless interconnect system.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128278953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397826
M. Camponeschi, A. Bevilacqua, P. Andreani
{"title":"Analysis and design of a low-power single-stage CMOS wireless receiver","authors":"M. Camponeschi, A. Bevilacqua, P. Andreani","doi":"10.1109/NORCHP.2009.5397826","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397826","url":null,"abstract":"The thorough analysis and the design of a complete 2.2 GHz quadrature receiver front-end suited for low-power applications is reported in this work. The circuit, built in a 90nm CMOS process, features a stacked single-ended low-noise amplifier and a self-oscillating mixer. The oscillator LC tank is designed to provide gain at low frequency without decreasing the quality factor at the oscillating frequency. A careful analysis shows that the parasitic capacitances at the output nodes ultimately limit the achievable conversion gain. Measurements show a conversion gain of 27.1 dB with a 14MHz bandwidth, a noise figure ranging from 12.4 to 13.2 dB with a flicker corner frequency of 200 kHz and an input referred 1 dB compression point of −23.7 dBm. The circuit draws only 1.3mA from a 1.0V supply.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125338581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397842
H. Aghababa, B. Forouzandeh, H. Dehghan, A. Afzali-Kusha
{"title":"A robust method to estimate Power and Delay for Digital Integrated Circuits","authors":"H. Aghababa, B. Forouzandeh, H. Dehghan, A. Afzali-Kusha","doi":"10.1109/NORCHP.2009.5397842","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397842","url":null,"abstract":"Advancements in nano-scale Integrated Circuits manufacturing technology has resulted in variability of performance metrics. The performance parameters such as Power and Delay are no longer represented deterministically. As a result, circuit designers and manufacturers need to make use of statistical analysis to estimate performance of Integrated Circuits. In this paper we present a new methodology to increase the accuracy of estimation compared to prior methods. We introduce Bayesian analysis as a powerful mathematical and statistical approach to incorporate the prior observations in calculating the Probability Density Function (PDF) of performance parameters like Power and Delay. We apply this technique on a few Digital Gates and compare the results with previous methods. We also introduce Bayesian analysis as a powerful method to update the PDF of performance parameters. Finally, we demonstrate how this statistical approach could supersede the approaches established on Frequentist analysis so as to achieve a more accurate estimation on Power and Delay for Digital Integrated Circuits.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"9 2-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397831
Xiaowen Wu, Yilang Wu, Ling Wang, Xiaoqing Yang
{"title":"QoS router with both soft and hard guarantee for Network-on-Chip","authors":"Xiaowen Wu, Yilang Wu, Ling Wang, Xiaoqing Yang","doi":"10.1109/NORCHP.2009.5397831","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397831","url":null,"abstract":"A GALS Networks-on-Chip (NoC) router with QoS support is presented. It supports multi-levels of QoS including hard guarantees (Hard GT)and statistical guarantees(Soft GT). In hard GT, novel Rate-control schedule is adopted to decouple the relationship between bandwidth and delay. And then, different from other routers whose bandwidth left was absorbed by only BE packets, we also support soft GT to further maximize network performance. In Soft GT, VC is dynamically allocated and performance is improved. Simulation shows that our router supports QoS well with little overhead.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"30 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113975931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397822
W. H. Minhass, J. Oberg, I. Sander
{"title":"Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol","authors":"W. H. Minhass, J. Oberg, I. Sander","doi":"10.1109/NORCHP.2009.5397822","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397822","url":null,"abstract":"Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance the NoC-grid off-chip is needed. In this paper, we present such a method. As a proof of concept, the protocol is implemented on a 4 by 4 Mesh NoC, with NIOS II CPU cores as nodes, partitioned across four separate Altera FPGA boards, each board hosting a Quad-Core (2×2) NoC, operating on a local 50 MHz clock. The inter-chip communication protocol uses asynchronous clock bridges, with a throughput of 50 Mbps (~lMFlit/s) and is completely scalable. The NoC has an onboard throughput of 650 Mbps (12.5 MFlit/s). Each Quad-Core uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of the Stratix II FPGAs. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with each other over the NoC.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2009 NORCHIPPub Date : 2009-11-01DOI: 10.1109/NORCHP.2009.5397814
R. Kanth, A. Singhal, P. Liljeberg, H. Tenhunen
{"title":"Analysis, design and development of novel, low profile microstrip antenna for satellite navigation","authors":"R. Kanth, A. Singhal, P. Liljeberg, H. Tenhunen","doi":"10.1109/NORCHP.2009.5397814","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397814","url":null,"abstract":"International Telecommunication Union Radio Communication Sector ( ITU-R) has assigned 1.176 GHz and 2.487 GHz respectively in L and S band to Regional Navigational Satellite System (RNSS) for satellite navigation purpose. In this paper attempt has been made to design a novel, low profile compact microstrip antenna which achieves required specification such as gain of −4dBi up to ±50° and bandwidth of 30 MHz. The design of L band antenna was carried out using Ansoft Designer Version 2 software and was fabricated and measured the required performance of antenna in terms of its return loss, VSWR and gain radiation pattern. The return loss of the developed antenna was measured with the vector network analyzer and its gain radiation pattern in anechoic chamber and the performance of its measurements were compared with the analyzed results.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}