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Hardware implementation of mapper for faster-than-Nyquist signaling transmitter 比奈奎斯特信号发送器更快的映射器的硬件实现
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397801
D. Dasalukunte, F. Rusek, V. Owall, K. Ananthanarayanan, M. Kandasamy
{"title":"Hardware implementation of mapper for faster-than-Nyquist signaling transmitter","authors":"D. Dasalukunte, F. Rusek, V. Owall, K. Ananthanarayanan, M. Kandasamy","doi":"10.1109/NORCHP.2009.5397801","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397801","url":null,"abstract":"This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is look-up table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a random access memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130 nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124074262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A digital back-end of energy detection UWB impulse radio receiver 一种数字后端能量检测超宽带脉冲无线电接收机
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397794
Z. Zou, F. Jonsson, Lirong Zheng, H. Tenhunen
{"title":"A digital back-end of energy detection UWB impulse radio receiver","authors":"Z. Zou, F. Jonsson, Lirong Zheng, H. Tenhunen","doi":"10.1109/NORCHP.2009.5397794","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397794","url":null,"abstract":"This paper presents a digital back-end design for energy detection IR-UWB receivers which can be adopted in RFID and wireless sensor applications. A baseband processor is designed on the basis of a novel synchronization and estimation algorithm. It reduces implementation complexity and energy consumption. A programmable timing circuitry with 1.04ns phase resolution is also devised in this work. The digital back-end is implemented in UMC 90nm process, with 222µW power and 140*220µm2 die area.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117133974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Power reduction through adaptive data compression in Network-on-Chip architectures 在片上网络架构中通过自适应数据压缩来降低功耗
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397810
Mehdi Taassori, Mohsen Mossavi
{"title":"Power reduction through adaptive data compression in Network-on-Chip architectures","authors":"Mehdi Taassori, Mohsen Mossavi","doi":"10.1109/NORCHP.2009.5397810","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397810","url":null,"abstract":"In this paper we present an adaptive compression technique that reduce the power consumption when compare to the compressed and original uncompressed data. We adapt a compression method by distances between transmitter and receiver. We show that compressing data for all of the distances is not useful. Experimental results indicate that our approach save power consumption as much as 24%. We also add encoding approach to compressor, to achieve both bit and transition reduction. Experimental results show that by using coder and decoder and adapting part, power saving can reach up to 30%.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"55 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120923018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multi-dimensional routing algorithms for congestion minimization in Network-on-Chip 片上网络中减少拥塞的多维路由算法
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397832
K. Somasundaram, J. Plosila
{"title":"Multi-dimensional routing algorithms for congestion minimization in Network-on-Chip","authors":"K. Somasundaram, J. Plosila","doi":"10.1109/NORCHP.2009.5397832","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397832","url":null,"abstract":"In Network on Chip (NoC), the traditional routing schemes are routing the network through a single path or multiple paths from one source node to a destination node, which will minimize the congestion in the routing architecture. Though these routing algorithms are moderately efficient, but time dependent. To reduce overall data packet transmission time in the network, we consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, we have shown a multi-dimensional path routing algorithm for minimizing the congestion in NoC with deadlock free.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-level continuous-time sigma delta design in Matlab/Simulink Matlab/Simulink中的高级连续σ δ设计
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397821
R. Kaald, I. Løkken, B. Hernes, T. Saether
{"title":"High-level continuous-time sigma delta design in Matlab/Simulink","authors":"R. Kaald, I. Løkken, B. Hernes, T. Saether","doi":"10.1109/NORCHP.2009.5397821","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397821","url":null,"abstract":"This paper presents a framework for behavioral simulations of continuous time delta-sigma modulators (CTSD) developed in Matlab/Simulink. Error sources in CTSD designs are reviewed and it is explained how sub-module specifications can be derived from a system-level target performance. The paper also discusses considerations of importance when using Simulink for CTSD modelling, like the choice of solver and simulation speed optimization. An example CTSD design is used throughout to illustrate the results and error models.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116865259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Application specific IP placement for on-chip distributed architectures 芯片上分布式架构的应用程序特定IP放置
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397804
Khalid Latif, H. Tenhunen, T. Seceleanu
{"title":"Application specific IP placement for on-chip distributed architectures","authors":"Khalid Latif, H. Tenhunen, T. Seceleanu","doi":"10.1109/NORCHP.2009.5397804","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397804","url":null,"abstract":"In this paper we approach the performance aspects of MPSoC platforms, from the point of view of IP placement with the focus on Network-on-Chip(NoC). Proper IP placement is important for several time-dependent applications such as video and voice where traffic must be delivered on time in order to operate properly. Proper placement of IPs can lower the traffic congestion, improve overall execution time and power consumption. We have suggested a new criteria for the prioritization of IPs regarding placement. Based on that criteria, we implemented an algorithm for IP placement.The running example is represented by mapping of H.264 encoder application on a NoC mesh. Allocation of processing elements on the platform, topology and communication mechanism are the main topics described here.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123995238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sign-bit based architecture for OFDM Acquisition for multiple-standards 基于符号位的多标准OFDM采集体系结构
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397841
I. Diaz, L. Wilhelmsson, J. Rodrigues, T. Olsson, V. Owall
{"title":"Sign-bit based architecture for OFDM Acquisition for multiple-standards","authors":"I. Diaz, L. Wilhelmsson, J. Rodrigues, T. Olsson, V. Owall","doi":"10.1109/NORCHP.2009.5397841","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397841","url":null,"abstract":"This paper presents a hardware mapping of an auto-correlator for Orthogonal Frequency Division Multiplexing stage for three radio standards: LTE, DVB-H, and IEEE 802.11n. Hardware cost is minimized by using only the sign bit in the autocorrelation function. The frequency offset estimation procedure is dramatically simplified by reducing the phase of the envelope to ¿/2 resolution, which in turn reduces the need of specialized components. The architecture is synthesized towards a 65 nm low-leakage high threshold standard cell CMOS library. The 1-bit architecture reports an area reduction of 90% for memories, 56% for the logic and a power dissipation reduction of 35%, when compared to an identical 8-bit implementation. The approximate area occupied by the architecture is 0.03 mm2. Power simulations for IEEE 802.11n packet reports a power dissipation of 42 ¿W.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116837710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Impact of intra-die random variations on clock tree 芯片内随机变化对时钟树的影响
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397809
Tarun Chawla, Sébastien Marchal, A. Amara, A. Vladimirescu
{"title":"Impact of intra-die random variations on clock tree","authors":"Tarun Chawla, Sébastien Marchal, A. Amara, A. Vladimirescu","doi":"10.1109/NORCHP.2009.5397809","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397809","url":null,"abstract":"Random intra-die variation is an ever-increasing concern in the microelectronics industry. Analysis solutions available today are complex to implement industrially. Most works on intra-die variations concentrate on systematic mismatch that is ameliorated through manufacturing improvements (e.g. regularity improvement in Design Rule Manual). Statistical static timing analysis (SSTA) is said to be a good estimator of random intra-die variations but lacks ease of deployment and requires lots of effort in characterizing the libraries. Even then, extensive analysis tools do not necessarily provide insights about the differences between the impact on various cells and their context. In this work, we have tried to find a rapidly implementable solution in commercial Computer Aided Design (CAD) tools using industrial models to reduce the impact of random intra-die variations at cell level and to find the basic set of parameters on which to base the usability of standard cells. We have characterized the impact of random variations on some basic cells used in clock like structures to achieve the said purpose.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An architecture for calculation of the distance transform based on Mathematical Morphology 一种基于数学形态学的距离变换计算体系
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397819
H. Hedberg, V. Owall
{"title":"An architecture for calculation of the distance transform based on Mathematical Morphology","authors":"H. Hedberg, V. Owall","doi":"10.1109/NORCHP.2009.5397819","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397819","url":null,"abstract":"This paper presents a hardware architecture for calculating the city-block and chessboard distance transform on binary images. It is based on applying multiple morphological erosions and adding the result, enabling both processing pixels in raster scan order and a deterministic execution time. Which distance metric to be calculated is determined by the shape of the structuring element, i.e. diamonds for the city-block and squares for the chessboard. These properties together with a low memory requirement make the architecture applicable in any streaming data real-time embedded system environment with hard timing constraints, e.g. set by the frame rate. Depending on the application, a priori knowledge of the maximum size of the clusters may be used to reduce execution time and memory requirement even further. The architecture has been implemented for both FPGA and ASIC in an embedded system environment with an image resolution of 320 × 240 at a frame rate of 25 fps, running at 100 MHz and 454 MHz, respectively.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115285922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Specification-driven testbench development for synchronous parallel-pipeline designs 同步并行管道设计的规范驱动测试平台开发
2009 NORCHIP Pub Date : 2009-11-01 DOI: 10.1109/NORCHP.2009.5397808
M. Chupilko, A. Kamkin
{"title":"Specification-driven testbench development for synchronous parallel-pipeline designs","authors":"M. Chupilko, A. Kamkin","doi":"10.1109/NORCHP.2009.5397808","DOIUrl":"https://doi.org/10.1109/NORCHP.2009.5397808","url":null,"abstract":"In this paper an approach to testbench development for synchronous parallel-pipeline designs is considered. The approach is based on cycle-accurate formal specifications of a design under verification. Specifications include descriptions of control flow graphs of the design's operations and definitions of the microoperations with the help of Hoare triples. The approach allows to automate testbench development for complex synchronous designs with control flow branching and parallel starting operations.","PeriodicalId":308859,"journal":{"name":"2009 NORCHIP","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126189443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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