Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

Abstract

32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triple-well 90 nm CMOS process. Measurements also demonstrate that the digital abstraction may be maintained for basic building blocks under the presence of stuck-open faults and defect transistors, for a redundancy factor, R, of only 2. R = 2 combined with shorted driven nodes is lower than the traditional R=3 in combination with majority voting.