Physical design and reliability issues in nanoscale analog CMOS technologies

Abstract

In nanoscale analog CMOS design there is no good substitute for understanding reliability stress factors or the many effects related to the circuit physical layout which can cause significant design-for-reliability (DFR), performance (DFP), or manufacturability (DFM) yield degradation. Circuit simulation tools presently lack the capability to predict the effect of several stress and reliability effects, including TDDB, HCI, NBTI, etc. Physical design deficiencies found after post-layout-extraction result in re-layout and a waste of the industries most valuable commodity: time to market. This paper presents an overview of these effects on nanoscale analog circuit design and also explores how to alter device geometries to mitigate them. Additionally, methods for extending device terminal voltage limits under certain conditions beyond foundry-specified voltage limits will be explored.