{"title":"Implementation of Elliptic Curve Cryptography over a Server-Clie|nt network","authors":"B. S. B.","doi":"10.1109/ICDCS48716.2020.243562","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243562","url":null,"abstract":"With the rapid development and advancement in the field of cryptographic technology, people find various methods to hack information. For secured data communication, cryptography is one of the techniques. It fundamentally deals with encryption and decryption of a given data. ECC and RSA are two such methods of public key cryptography. The main advantage of ECC when compared with RSA is that it gives fairly equal amount of protection and safety against hackers even for lesser bit size of keys, hence reducing the computation power and bandwidth. This paper discusses the implementation of ECC using ElGamal algorithm over a server-client framework. Implementation is performed on Python IDE JetBrains PyCharm.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Analysis of LIM Hybrid MTJ/CMOS Logic Gates","authors":"Prashanth Barla, Deeksha Shet, V. Joshi, S. Bhat","doi":"10.1109/ICDCS48716.2020.243544","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243544","url":null,"abstract":"Surge in the power dissipation due to increased leakage current has become one of the major concern in conventional CMOS VLSI design because of reduced transistor size, lower threshold voltage and lower supply voltage. To alleviate this, we have designed hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on logic-in-memory (LIM) structure for various logic gates such as NAND/AND, NOR/OR and XNOR/XOR. This paper investigates the performance of hybrid gates and the results are compared with the conventional CMOS based gates in-terms of power, delay and device count. Hybrid gates designed in this paper are not only non-volatile in nature due to the use of MTJs but also they are found superior than the conventional CMOS circuits by dissipating less power and occupying smaller die area.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Assessment of Polarity Tunable- Ferroelectric-Field Effect Transistor at High Temperature —Part I","authors":"P. Pandey, H. Kaur","doi":"10.1109/ICDCS48716.2020.243574","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243574","url":null,"abstract":"In the present article, a comprehensive study has been carried out to assess the high temperature performance of Polarity Tunable-Ferroelectric-Field Effect Transistor (PT-FE-FET). Owing to the presence of ferroelectric layer in gate-stack of PT-FE-FET, the device offers super-steep subthreshold characteristics along with steep surface potential characteristics and ON-state current for both n- and p- operational modes. Even at elevated temperatures, the proposed device continues to render superior device performance and is immune towards high temperatures such as 400 K. Thus, the proposed device is a suitable contender for energy-efficient high temperature applications.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Heterojunction Tunnel Field Effect Transistors – A Detailed Review","authors":"J. E. Jeyanthi, T. Arunsamuel","doi":"10.1109/ICDCS48716.2020.243609","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243609","url":null,"abstract":"Tunnel FET(TFET) can provide ultra-low quiescent (~pA) current. Some of the essential parameters for determining the characteristics of TFET are high ION current, constrained Subthreshold slope value, and reduced ambipolar leakage. TFET experiences a sub-threshold decrease of less than 60mV/decade in the process of the sub-threshold slope and hence higher transconductance per bias current than MOSFET. This article would be beneficial to get a review of various device structures and their performances of Tunnel FET. In this paper, we examined the multiple TFET device structures and compared their performances for attaining the desired ION/IOFF.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Analysis of Radio Frequency (RF) Low Noise Amplifier (LNA) with various Transistor Configurations","authors":"Mayuresh Joshi, R. Mathew, Pallabi Sarkar, Arya Dutt, Sanjana Tiwari, Prakhar Nigam","doi":"10.1109/ICDCS48716.2020.243555","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243555","url":null,"abstract":"In a radio frequency (RF) transceiver, low noise amplifier (LNA) plays a critical role in determining the receiver performance. This paper elucidates the design of an LNA for optimizing its gain, noise figure and stability factor with different transistor configurations in the frequency range of 5-6 GHz. Design-optimization of LNA has been performed with standard transistor (BJT and MOSFET) files in circuit simulation software. For comparison we have considered the following configurations of LNA: (i) a single stage npn BJT LNA, (ii) npn BJT and NMOS cascode LNA, and (iii) npn BJT and CMOS cascode LNA. Simulation results show that compared to other configurations npn BJT-NMOS cascode LNA depicts the highest gain of 20.42 dB and the lowest noise figure of 0.25. On the other hand, npn BJT-CMOS cascode LNA demonstrates the highest stability factor of 1.07 followed by npn BJT LNA and npn BJT-NMOS cascode LNA configurations respectively. Further improvement in the LNA performance metrics is feasible by parametric optimization of transistor parameters and passive elements in the matching network.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"116 51","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Skin Cancer Detection Using Gray Level Co-occurrence Matrix Feature Processing","authors":"Swati Jayade, D. Ingole, M. D. Ingole","doi":"10.1109/ICDCS48716.2020.243546","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243546","url":null,"abstract":"At present time, skin cancer is becoming common explanation for death in citizenry . Often when body exposed to the daylight , it's going to causes carcinoma it's a abnormal growth of skin cells within the physical body . Generally most of the skin cancers are often cured if they're detected in early of its stage. Hence if it's detected early and fast the lifetime of patient are often saved. General method for diagnosis of carcinoma is biopsy. In biopsy affected somatic cell are removed which sample are sent for laboratory testing. it's tedious and time consuming process. So there's a requirement of auto software aided system for accurate and fast processing. it'll empower target understanding by making utilization of quantitative parameters. during this system features of cancerous region are extracted and support vector machine (SVM) classifier is employed to detect carcinoma . This diagnosing methodology uses the pictures taken by dermoscopy, then some image preprocessing is completed to reinforce the standard and take away the noise from images followed by segmentation using thresholding technique. To extract the features of image GLCM methodology is implemented, these features are given as an input to the classifier. Classifier will categories the given image into either of cancerous or non-cancerous type accordingly. The performance analysis indicates that this method outperforms as compared to the prevailing systems as its accuracy is 94.05%.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132953249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sabari. M, Aswinth. P, Karthik. T, Bharath kumar. C
{"title":"Water Quality Monitoring System Based On IoT","authors":"Sabari. M, Aswinth. P, Karthik. T, Bharath kumar. C","doi":"10.1109/ICDCS48716.2020.243598","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243598","url":null,"abstract":"According to data issued by human rights commission, 20 million people are still drinking contaminated water in our country. We have to continuously monitor water quality parameters to reduce water related diseases and to avoid water pollution. In preliminary methods of water monitoring, data are collected manually from various sources. This needs ample time and rigorous manual effort. To overcome these problems we have to adopt new methods for water monitoring. The main aim of this work is to design a system to continuously monitor the water quality parameters based on the concept of IoT. The proposed model employs various sensors to measure the required parameters. With the help of a core controller, the measured parameter values from sensors are processed. Arduino is the core controller used for the entire model. Using a Wi-Fi module, measured data from sensors are viewed on the cloud platform.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Implementation of 32-bit Functional Unit for RISC architecture applications","authors":"Rashmi Samanth, Ashwini Amin, S. G. Nayak","doi":"10.1109/ICDCS48716.2020.243545","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243545","url":null,"abstract":"This paper presents the design and implementation of 32-bit Functional unit which is used for RISC based processor. This includes designing of processor modules such as Arithmetic and Logic unit (ALU) which realizes addition, subtraction, multiplication, shifting and code conversion by suitable control units and data paths. Multiplexers are used for selecting various operations based on the control inputs. These functional blocks are developed using the Hardware Description Language (HDL). Simulation and synthesis of each block is carried using Xilinx ISE to analyze the results. Results of proposed design has been compared with the conventional Microprocessor without interlocked Pipeline Stages (MIPS) which shows reduction in power dissipation by 30.449%, area by 6% and delay by 34.49%.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126372081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Praveen Pal, Yogesh Pratap, Mridula Gupta, S. Kabra, Himani Dua Sehgal
{"title":"Performance analysis of ScAlN/GaN High Electron Mobility Transistor (HEMT) for biosensing application","authors":"Praveen Pal, Yogesh Pratap, Mridula Gupta, S. Kabra, Himani Dua Sehgal","doi":"10.1109/ICDCS48716.2020.243581","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243581","url":null,"abstract":"In this work ScA1N film has been used to serve as a barrier in III-Nitride heterojunctions. The reduced lattice mismatch on GaN and better polarization properties of ScxA11-xN makes this material a promising candidate for RF biosensing applications. Therefore, in this work a cantilever type structure has been used to design ScA1N/GaN based biosensor. The maximum drain on sensitivity which has been achieved in this work is 0.421 for keratin. Maximum change of 2V in threshold voltage and 0.00284A drain current has been observed for keratin. The work has been performed on ScAlN/GaN HEMT device using ATLAS technology computer-aided design (TCAD) tool. The sensitivity parameters which have been used to detect the biomolecules are drain current, threshold voltage, transconductance and subthreshold current. Drains on sensitivity and threshold sensitivity of the device have also been evaluated.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126489463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault Detection and Diagnosis of Multi-Phase Induction Motor Drives Using MFRF Technique","authors":"Balamurugan Annamalai, S. Swaminathan","doi":"10.1109/ICDCS48716.2020.243590","DOIUrl":"https://doi.org/10.1109/ICDCS48716.2020.243590","url":null,"abstract":"In the dissertation, a hybrid technique based on detection and diagnosis of fault in multi-phase induction motor (IM) is performed. The present technique is the hybridization of Moth Flame optimization (MFO) and Random Forest algorithm (RFA) and it is named as MFRF method. The multiphase IM is evaluated under normal conditions in the initial period. The fault is maintained in multi-phase IM as well as characteristics of system are observed. In the defective period, signals are scaled, that may seen as waveforms are distorted. Distorted waveforms are made up of various frequency methods are required to represent as frequency of time domain as evaluation of failure. IM. The proposed technique is performed in MATLAB/Simulink platform. Implementation of established technique is contrasted to existing methods, like ANN, S-Transform and GBDT. The statistical measures are determined to demonstrate the successfulness of established technique, like precision, sensitivity and specificity, mean median and standard deviation.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130681027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}