63rd Device Research Conference Digest, 2005. DRC '05.最新文献_第5页

Enhancement-mode InAlAs/InGaAs/InP HEMTs with Ir-based gate metallization 具有ir基栅金属化的增强型InAlAs/InGaAs/InP hemt

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553147

S. Kim, I. Adesida

{"title":"Enhancement-mode InAlAs/InGaAs/InP HEMTs with Ir-based gate metallization","authors":"S. Kim, I. Adesida","doi":"10.1109/DRC.2005.1553147","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553147","url":null,"abstract":"The reliability of high electron mobility transistors (HEMTs) significantly depends on the stability of the gate Schottky contact to the semiconductor. Gate sinking during the fabrication and device operation alters transconductance, gate capacitance, and threshold voltage, which are crucial device parameters for modeling HEMT devices and designing circuits. In particular for enhancement-mode InAlAs/InGaAs/InP HEMTs (eHEMTs) where thermally-treated Pt is utilized as the gate metallization, thermal stability has always constituted a problem due to the diffusion of Pt. Although aspects of this diffusion are utilized to enhance e-mode behavior, no quantitative measurements have been conducted to estimate the diffusion depth of Pt in InAlAs. Further, it would be preferable to develop a metallization scheme where the Schottky contact barrier height is similar to that of Pt but with a much lower diffusivity. To this end, we have developed a gate metal structure based on Ir for InAlAs/InGaAs/InP HEMTs and investigated its thermal stability in comparison to the conventional Pt-based contact. A 0.15 um-gatelength eHEMT utilizing Ir/Ti/Pt/Au gate was fabricated to demonstrate the potential of Ir-based gate technology","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122429835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast high-k AIN MONOS memory with large memory window and good retention 快速高k AIN MONOS内存，内存窗口大，保留率好

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553074

C. Lai, C.C. Huang, K. Chiang, H. Kao, W. Chen, A. Chin, C. Chi

引用次数: 4

Cat-CVD SiN insulated-gate AlGaN/GaN HFETs with 163 GHz f/sub T/ and 184 GHz f/sub max/ 具有163 GHz f/sub T/和184 GHz f/sub max/的Cat-CVD SiN绝缘栅AlGaN/GaN hfet

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553161

M. Higashiwaki, T. Matsui, T. Mimura

引用次数: 7

Top-gated field effect devices using oxidized silicon nanowires 氧化硅纳米线顶门控场效应器件

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553101

Yanfeng Wang, K. Lew, James B. Mattzela, J. Redwing, T. Mayer

{"title":"Top-gated field effect devices using oxidized silicon nanowires","authors":"Yanfeng Wang, K. Lew, James B. Mattzela, J. Redwing, T. Mayer","doi":"10.1109/DRC.2005.1553101","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553101","url":null,"abstract":"The Si nanowires (SiNWs) used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH 4 in H2 as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH3) as the n-type dopant. The ratio of TMB or PH3 to SiH4 was varied from 0 to 10-2 to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700degC for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the -10 nm thick SiO2 shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 mum long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO2 shell, which served as the top gate dielectric. The n++ Si substrate coated with 100 nm of LPCVD Si3N4 was used as a back gate in these structures","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Tunnel junctions in GaN/AlN for optoelectronic applications 光电应用中GaN/AlN的隧道结

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553039

M. Grundmann, J. Speck, U. Mishra

引用次数: 3

Proposal of a spintronics-based polarization detector 一种基于自旋电子学的偏振探测器的设计

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553159

L. Cywinski, H. Dery, L. Sham

引用次数: 1

Vertical high mobility wrap-gated inas nanowire transistor 垂直高迁移率包裹门控纳米线晶体管

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553100

T. Bryllert, L. Samuelson, L. Jensen, L. Wernersson

引用次数: 45

Switching characteristics of high-breakdown voltage AlGaN/GaN HEMTs 高击穿电压AlGaN/GaN hemt的开关特性

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553115

Y. Dora, C. Suh, A. Chakraborty, S. Heikman, S. Chandrasekaran, V. Mehrotraa, U. Mishra

引用次数: 6

Energy level consideration of source/channel/drain for performance enhancements of N- and P-channel organic FETs 提高N沟道和p沟道有机场效应管性能的源/沟道/漏极能级考虑

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553078

T. Yokoyama, T. Nishimura, K. Kita, K. Kyuno, A. Toriumi

引用次数: 0

Molecular beam epitaxy of Pr/sub 2/O/sub 3/on Si Pr/sub 2/O/sub 3/在Si上的分子束外延

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553068

B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog

{"title":"Molecular beam epitaxy of Pr/sub 2/O/sub 3/on Si","authors":"B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog","doi":"10.1109/DRC.2005.1553068","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553068","url":null,"abstract":"Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0