63rd Device Research Conference Digest, 2005. DRC '05.最新文献_第4页

Monte carlo study of germanium N- and P- MOSFETs 锗N-和P- mosfet的蒙特卡罗研究

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553065

B. Ghosh, Xiao-Feng Fan, L. Register, S. Banerjee

{"title":"Monte carlo study of germanium N- and P- MOSFETs","authors":"B. Ghosh, Xiao-Feng Fan, L. Register, S. Banerjee","doi":"10.1109/DRC.2005.1553065","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553065","url":null,"abstract":"As device dimensions are being scaled to their ultimate limits, channel mobility engineering seems to offer one of the best prospects of improved performance of metal oxide semiconductor field effect transistors (MOSFETs). In fact, new materials, such as Ge, with higher effective mobilities of electrons (2times) and holes (4times) than in Si are already being explored to increase the drive currents in MOSFETs. In addition, by straining the Ge channels, it is possible to further increase the mobilities of the holes. However, how this advantage in mobility translates to improved drive current in the short-channel length MOSFETs is not completely clear. For example, in the ballistic limit, it is thermal velocity that matters (Lundstrom, 1997) and these are comparable for Si and Ge. Although, there have been reports from some experimental and theoretical (in the ballistic limit) studies of the mobility and drive current enhancements of unstrained and strained Ge channel MOSFETs over Si MOSFETs, no Monte Carlo simulation taking into account full band structure, scattering, non local field effects, etc., has so far been been performed. The aim of this work was to perform a full band Monte Carlo simulation study of unstrained Ge bulk N- and P- MOSFETs and strained Ge bulk PMOSFETs and compare with their Si counterparts. Since biaxial strain along the (100) plane in Ge does not break the degeneracy of the conduction band L valleys of Ge, we have not considered strained Ge NMOSFETs","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125227767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Current status of chalcogenide phase change memory 硫族相变存储器的现状

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553042

G. Atwood, R. Bez

{"title":"Current status of chalcogenide phase change memory","authors":"G. Atwood, R. Bez","doi":"10.1109/DRC.2005.1553042","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553042","url":null,"abstract":"Non-volatile memories (NVM) are playing an important role in the semiconductor market, thanks in particular to flash which is used mainly in cellular phones and other types of electronic portable equipment. In the coming years portable systems will demand even more NVM with high density and very high writing throughput for data storage application, or with fast random access for code execution. Flash memory has followed the scaling evolution, of the semiconductor map since its introduction in the late '80's but further scaling is becoming increasingly complex as some of the fundamental physical limitations are being approached. While continued research on floating gate techniques should extend the current flash technology capability through the end of this decade, there is increasing interest in new memory storage mechanisms and materials that have promise for scaling through at least the end of the next decade. Among the different NVM based on storage mechanisms alternative to the floating gate concept, phase-change memories (PCM), also called ovionic unified memory (OUM),is one of the most promising candidates, having the potential to improve the performance compared to flash as well as to be scalable beyond flash technology (Lai and Lowrey (2001), Lai (2003), Bez (2004)), In this review, the physics and operation of phase change memory is first presented, followed by discussion of current status of development. Finally, the scaling capability of the technology is absent","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain 具有NiSi/sub 2/[111]面状全硅化源极/漏极的亚10nm栅极长度金属/高k SOI mosfet

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553118

Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi

引用次数: 5

Increased reliability of a-Si TFT's deposited on clear plastic substrates at high temperatures 提高了透明塑料衬底上沉积的a-Si TFT在高温下的可靠性

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553094

K. Long, A. Kattamis, I. Cheng, H. Gleskova, S. Wagner, J. Sturm

引用次数: 2

Bi-layer artificial muscle valves for drug delivery devices 用于给药装置的双层人工肌肉瓣膜

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553089

H. Tsai, J. Zoval, M. Madou

引用次数: 0

Germanium sulfide-based solid electrolytes for non-volatile memory 非易失性存储器用硫化锗固体电解质

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553049

Muralikrishnan Balakrishnan, M. Kozicki, C. Gopalan, M. Mitkova

引用次数: 9

High performance low power 6.0 A HBT devices and circuits 高性能低功耗6.0 A HBT器件和电路

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553151

C. Monier, A. Cavus, R. Sandhu, D. Li, P. Nam, B. Chan, A. Oshiro, D. Matheson, A. Gutierrez-Aitken

引用次数: 2

All-organic active matrix oled display 全有机有源矩阵oled显示器

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553092

Lisong Zhou, Sungkyu Park, Bo Bai, Jie Sun, Sheng-Chu Wu, T. Jackson, S. Nelson, D. Freeman, Yongtaek Hong

引用次数: 1

Planar tunneling-coupled field-effect transistor for low-power mixed-signal applications 用于低功耗混合信号应用的平面隧道耦合场效应晶体管

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553148

J. Moon, K. Wang, R. Rajavel, S. Bui, D. Wong, D. Chow, J. Jenson

{"title":"Planar tunneling-coupled field-effect transistor for low-power mixed-signal applications","authors":"J. Moon, K. Wang, R. Rajavel, S. Bui, D. Wong, D. Chow, J. Jenson","doi":"10.1109/DRC.2005.1553148","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553148","url":null,"abstract":"In this paper, we report a prototype demonstration of room-temperature resonant tunneling-coupled transistors in FET layout (TCT), in which tunneling characteristics such as negative differential resistance (NDR) and peak current are directly controlled by surface Schottky gate with high gain and transconductance. Functionality of the device can also be switched between FET mode and tunneling transistor mode. The fabrication process is fully compatible with conventional FET processes, offering a fully integrable and scalable tunneling transistor technology. Prototype planar TCTs were fabricated with resonantly-coupled dual-channel InAlAs/InGaAs/InP HEMT heterostructures by providing independent electrical contacts to each channel. The current-voltage characteristics are determined by an interwell and intersubband tunneling. The fabrication process was done using an I-line Cannon stepper on full 3-inch wafers with implanted back-gates defined prior to MBE growth of closely-coupled dual-channel HEMT layers. The highest mobility of the closely-coupled dual-channel HEMT layers observed so far is 9600 cmWs at room temperature","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125688048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Higher k HfTaTiO gate dielectric with improved material and electrical characteristics 高k HfTaTiO栅极电介质，改善了材料和电学特性

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI: 10.1109/DRC.2005.1553129

N. Lu, H. Li, M. Gardner, D. Kwong

引用次数: 3