具有NiSi/sub 2/[111]面状全硅化源极/漏极的亚10nm栅极长度金属/高k SOI mosfet

63rd Device Research Conference Digest, 2005. DRC '05. Pub Date : 2005-06-22 DOI:10.1109/DRC.2005.1553118

Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi

{"title":"具有NiSi/sub 2/[111]面状全硅化源极/漏极的亚10nm栅极长度金属/高k SOI mosfet","authors":"Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi","doi":"10.1109/DRC.2005.1553118","DOIUrl":null,"url":null,"abstract":"Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain\",\"authors\":\"Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi\",\"doi\":\"10.1109/DRC.2005.1553118\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness\",\"PeriodicalId\":306160,\"journal\":{\"name\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"63rd Device Research Conference Digest, 2005. DRC '05.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2005.1553118\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

具有NiSi2/Si(111)面FUSI S/D的金属/高k SOI mosfet有望用于缩小至低于10 nm栅极长度的大规模器件。我们所开发的面结技术随着栅极长度的减小而更有效地工作。该器件概念可以应用于finfet等3D结构，并且还可以减轻SOI厚度的缩放

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain

Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

63rd Device Research Conference Digest, 2005. DRC '05.

自引率

0.00%

发文量