IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.最新文献_第3页

An efficient calibration technique for systematic current-mismatch of D/A converters 一种有效的D/A变换器系统电流失配校正技术

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183356

K. Baek, M. Choe, S. Kang

引用次数: 0

Random characterization of design automation algorithms 设计自动化算法的随机表征

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183493

Sandeep K. Kondapuram, P. Maurer

引用次数: 0

Power comparison of throughput optimized IC busses 吞吐量优化IC总线的功率比较

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183351

E. Malley, Ariel Salinas, Kareem Ismail, L. Pileggi

{"title":"Power comparison of throughput optimized IC busses","authors":"E. Malley, Ariel Salinas, Kareem Ismail, L. Pileggi","doi":"10.1109/ISVLSI.2003.1183351","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183351","url":null,"abstract":"Globally asynchronous bus designs are considered theoretically attractive for saving power. In this work we design and compare asynchronous and synchronous busses in 0.13um and 0.10um technologies based on bus-wires that are optimized for throughput per unit channel area. At high frequency the synchronous data bus wire power exceeds that for the asynchronous design due to the higher latch-repeater power. In contrast, the asynchronous bus control power is greater than the local synchronous clock power until a sufficient number of bus lines share the control line. Based on a reasonable switching activity factor for the lines (e.g. /spl sim/15%), however, a shared control line can be considered as switching continuously for 32 bits or more, while the bus is being utilized. The power benefits of asynchronous, therefore, are questionable for applications such as globally asynchronous locally synchronous (GALS) methodologies. Moreover, the distinction between asynchronous and synchronous is marginal if we further consider a synchronous control line with a local pulse-generation circuit to drive half-latch repeaters in the data bus path.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116183219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A framework for security on NoC technologies NoC技术安全框架

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183361

C. Gebotys, R. Gebotys

{"title":"A framework for security on NoC technologies","authors":"C. Gebotys, R. Gebotys","doi":"10.1109/ISVLSI.2003.1183361","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183361","url":null,"abstract":"Multiple heterogeneous processor cores, memory cores and application specific IP cores integrated in a communication network, also known as networks on chips (NoCs), will handle a large number of applications including security. Although NoCs offer more resistance to bus probing attacks, power/EM attacks and network snooping attacks are relevant. For the first time, a framework for security on NoC at both the network level (or transport layer) and at the core level (or application layer) is proposed. At the network level, each IP core has a security wrapper and a key-keeper core is included in the NoC, protecting encrypted private and public keys. Using this framework, unencrypted keys are prevented from leaving the cores and NoC. This is crucial to prevent untrusted software on or off the NoC from gaining access to keys. At the core level (application layer) the security framework is illustrated with software modification for resistance against power attacks with extremely low overheads in energy. With the emergence of secure IP cores in the market and nanometer technologies, a security framework for designing NoCs is crucial for supporting future wireless Internet enabled devices.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 69

Low power test set embedding based on phase shifters 基于移相器的低功耗测试集嵌入

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183367

M. Bellos, D. Kagaris, D. Nikolos

引用次数: 1

A novel technique for noise-tolerance in dynamic circuits 一种新的动态电路容噪技术

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183465

S. Goel, T. Darwish, M. Bayoumi

引用次数: 9

Getting high-performance silicon from system-level design 从系统级设计中获得高性能芯片

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183482

W. R. Davis

引用次数: 9

Peak power minimization through datapath scheduling 通过数据路径调度实现峰值功率最小化

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183362

S. Mohanty, N. Ranganathan, Sunil K. Chappidi

{"title":"Peak power minimization through datapath scheduling","authors":"S. Mohanty, N. Ranganathan, Sunil K. Chappidi","doi":"10.1109/ISVLSI.2003.1183362","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183362","url":null,"abstract":"In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132595605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

An architectural leakage power simulator for VHDL structural datapaths VHDL结构数据路径的架构泄漏功率模拟器

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183470

C. Gopalakrishnan, S. Katkoori

引用次数: 6

System design approach to power aware mobile computers 功率感知移动计算机的系统设计方法

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183359

Jolin M. Warren, T. Martin, A. Smailagic, D. Siewiorek

引用次数: 8