Peak power minimization through datapath scheduling

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI:10.1109/ISVLSI.2003.1183362

S. Mohanty, N. Ranganathan, Sunil K. Chappidi

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引用次数: 32

Abstract

In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.

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通过数据路径调度实现峰值功率最小化

在本文中，我们描述了新的整数线性规划模型和算法的数据路径调度，其目的是在保持性能的同时最小化峰值功率。第一种算法MVDFC结合了多个电源电压和动态频率时钟来降低峰值功率，而第二种算法MVMC则探索了多个电源电压和多周期。算法以不同工作电压下不同功能单元的数量和类型作为资源约束。通过估计所合成的数据路径电路的峰值功耗和功率延迟积(PDP)，研究了所提出的调度算法的有效性。该算法已应用于不同资源约束下的各种高级综合基准电路。实验结果表明，对于MVDFC，在各种资源约束下，使用两种电源电压水平(5.0V, 3.3V)，平均峰值功率降低约75%，平均PDP降低约60%。对于MVMC方案，在类似的资源约束下，平均峰值功率降低约36%，平均PDP降低约20%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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