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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.最新文献

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Fast and precise power prediction for combinational circuits 快速精确的组合电路功率预测
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-28 DOI: 10.1109/ISVLSI.2003.1183489
H. Li, J. Antonio, S. Dhall
{"title":"Fast and precise power prediction for combinational circuits","authors":"H. Li, J. Antonio, S. Dhall","doi":"10.1109/ISVLSI.2003.1183489","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183489","url":null,"abstract":"The power consumed by a combinational circuit is dictated by the switching activities of all signals associated with the circuit. An analytical approach is proposed for calculating signal activities for combinational circuits. The approach is based on a Markov chain signal model, and directly accounts for correlations present among the signals. The accuracy of the approach is verified by comparing signal activity values calculated using the proposed approach with corresponding values produced through simulation studies. It is also demonstrated that the proposed approach is computationally efficient.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Future challenges in VLSI system design VLSI系统设计的未来挑战
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-28 DOI: 10.1109/ISVLSI.2003.1183346
J. Fortes
{"title":"Future challenges in VLSI system design","authors":"J. Fortes","doi":"10.1109/ISVLSI.2003.1183346","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183346","url":null,"abstract":"In the current and coming decades VLSI design - which currently enables us to build million-transistor chips will become Gigascale (GSI) design and Terascale Scale Integration (TSI) design, respectively. In this context, \"gigascale\" and \"terascale\" signifies more than one billion and one trillion devices per chip, respectively. From a system design perspective, this increase in integration levels is qualitatively different from past integration improvements of similar magnitudes. In particular, manufacturing defects will increase, devices will get less reliable, interconnect will be orders of magnitude slower than transistors, new nanotechnologies will emerge, and signal and power management issues will be aggravated. It is plausible that new nanotechnologies will be used to complement or replace CMOS. This paper (and its presentation) discusses some of the unique system design challenges posed by anticipated nanoscale CMOS and molecular electronics technologies, and presents some ground-breaking suggestions of novel system-level approaches to deal with these challenges.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130493200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC) 工业/学术可配置片上系统(CSoC)的架构、内存和接口技术集成
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183360
J. Becker, M. Vorbach
{"title":"Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC)","authors":"J. Becker, M. Vorbach","doi":"10.1109/ISVLSI.2003.1183360","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183360","url":null,"abstract":"This paper describes the actual status and results of a dynamically configurable system-on-chip (CSoC) integration, consisting of a SPAR C-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable size from PACT XPP Technologies AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 /spl mu/m UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115455637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
Crosstalk noise analysis in ultra deep submicrometer technologies 超深亚微米技术中的串扰噪声分析
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183461
M. Elgamel, K. Tharmalingam, M. Bayoumi
{"title":"Crosstalk noise analysis in ultra deep submicrometer technologies","authors":"M. Elgamel, K. Tharmalingam, M. Bayoumi","doi":"10.1109/ISVLSI.2003.1183461","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183461","url":null,"abstract":"In ultra deep submicron (UDSM) circuit design, the interconnect delay and noise have become the dominant factors in determining circuit performance. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modern designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we analyze the effects of all known interconnect and driver parameters on the crosstalk peak noise, crosstalk noise pulse width, and the impact of coupling on aggressor delay. We consider parameters like spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, direction of the signals, wire width for both the aggressors and the victim wires. Also, we consider parameters like driver strength as several recent studies considered the simultaneous device and interconnect sizing.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing 基于符号布局描述和块参数探索、布局和全局路由相结合的布局感知模拟系统综合
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183495
Hua Tang, Hui Zhang, A. Doboli
{"title":"Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing","authors":"Hua Tang, Hui Zhang, A. Doboli","doi":"10.1109/ISVLSI.2003.1183495","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183495","url":null,"abstract":"This paper presents a new methodology for layout-aware synthesis of analog systems. The methodology combines block parameter exploration, block placement and global interconnect routing while maintaining an accurate perspective on the layout parasitics. An original system representation (called Layout Constraint Graphs - LCG) was developed for synthesis. The paper discusses how block parameter exploration, placement and global routing are expressed in terms of the LCG graph. AC and transient performances of each explored solution are obtained using SPICE simulations. Experiments show the generality of the synthesis methodology by providing results for several applications including filters and converters.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS 缩小PD-SOI CMOS浮体效应的新型电路
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183350
K. Das, Richard B. Brown
{"title":"Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS","authors":"K. Das, Richard B. Brown","doi":"10.1109/ISVLSI.2003.1183350","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183350","url":null,"abstract":"SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled V/sub DD/s. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 /spl mu/m PD-SOI process.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129319218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hardware-only compression to reduce cost and improve utilization of address buses 仅硬件压缩，以降低成本并提高地址总线的利用率
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183475
Jiangjiang Liu, N. Mahapatra, Krishnan Sundaresan
{"title":"Hardware-only compression to reduce cost and improve utilization of address buses","authors":"Jiangjiang Liu, N. Mahapatra, Krishnan Sundaresan","doi":"10.1109/ISVLSI.2003.1183475","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183475","url":null,"abstract":"Communication components (address, instruction, and data buses and associated hardware like I/O pins, pads, and buffers) are contributing increasingly to the area/cost and power consumption of microprocessor systems. To decrease costs due to address buses, we propose to use narrow widths for underutilized buses (hardware-only compression) to transmit information in multiple cycles. We analyze performance and power consumption overheads of hardware-only compression and investigate the use of \"address concatenation\" to mitigate performance loss and address offsets and XORs to reduce power consumption overheads.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Bouncing threads: merging a new execution model into a nanotechnology memory 弹跳线程:将新的执行模型合并到纳米技术内存中
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183349
S. E. Murphy, Arun Rodrigues, Charles A. Giefer, P. Kogge
{"title":"Bouncing threads: merging a new execution model into a nanotechnology memory","authors":"S. E. Murphy, Arun Rodrigues, Charles A. Giefer, P. Kogge","doi":"10.1109/ISVLSI.2003.1183349","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183349","url":null,"abstract":"The need for small, high speed, low power computers as the end of Moore's law approaches is driving research into nanotechnology. These novel devices have significantly different properties than traditional MOS devices and require new design methodologies, which in turn provide exciting architectural opportunities. The H-memory is a design developed for a particular nanotechnology, quantum-dot cellular automata. We propose a new execution model that merges with the H-memory to exploit the characteristics of this nanotechnology by distributing the functionality of the CPU throughout the memory structure.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123612464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters 用于0.07 /spl mu/m CMOS闪存A/D转换器的量子电压比较器
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183500
Jincheol Yoo, Kyusun Choi, J. Ghaznavi
{"title":"Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters","authors":"Jincheol Yoo, Kyusun Choi, J. Ghaznavi","doi":"10.1109/ISVLSI.2003.1183500","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183500","url":null,"abstract":"This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Supply voltage scalable system design using self-timed circuits 采用自定时电路的供电电压可扩展系统设计
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183368
W. Kuang, J. Yuan, A. Ejnioui
{"title":"Supply voltage scalable system design using self-timed circuits","authors":"W. Kuang, J. Yuan, A. Ejnioui","doi":"10.1109/ISVLSI.2003.1183368","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183368","url":null,"abstract":"Supply voltage scalable system design for low power is investigated using self-timed circuits in this paper. Two architectures are proposed to achieve supply voltage scalability, for preserved quality and energy-quality tradeoff respectively, In the first architecture, the supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement and processing quality. In the second one, further energy saving is achieved at the cost of signal-noise-ratio loss in digital signal processing when an ultra-low supply voltage is applied. Cadence simulation shows the effectiveness for both architectures. More than 40% to 70% power can be saved by introducing -150 to -10 dB error in a case study: speech signal processing.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124697724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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