Hardware-only compression to reduce cost and improve utilization of address buses

Abstract

Communication components (address, instruction, and data buses and associated hardware like I/O pins, pads, and buffers) are contributing increasingly to the area/cost and power consumption of microprocessor systems. To decrease costs due to address buses, we propose to use narrow widths for underutilized buses (hardware-only compression) to transmit information in multiple cycles. We analyze performance and power consumption overheads of hardware-only compression and investigate the use of "address concatenation" to mitigate performance loss and address offsets and XORs to reduce power consumption overheads.