Future challenges in VLSI system design

Abstract

In the current and coming decades VLSI design - which currently enables us to build million-transistor chips will become Gigascale (GSI) design and Terascale Scale Integration (TSI) design, respectively. In this context, "gigascale" and "terascale" signifies more than one billion and one trillion devices per chip, respectively. From a system design perspective, this increase in integration levels is qualitatively different from past integration improvements of similar magnitudes. In particular, manufacturing defects will increase, devices will get less reliable, interconnect will be orders of magnitude slower than transistors, new nanotechnologies will emerge, and signal and power management issues will be aggravated. It is plausible that new nanotechnologies will be used to complement or replace CMOS. This paper (and its presentation) discusses some of the unique system design challenges posed by anticipated nanoscale CMOS and molecular electronics technologies, and presents some ground-breaking suggestions of novel system-level approaches to deal with these challenges.