Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters

Jincheol Yoo, Kyusun Choi, J. Ghaznavi
{"title":"Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters","authors":"Jincheol Yoo, Kyusun Choi, J. Ghaznavi","doi":"10.1109/ISVLSI.2003.1183500","DOIUrl":null,"url":null,"abstract":"This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28

Abstract

This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.
用于0.07 /spl mu/m CMOS闪存A/D转换器的量子电压比较器
本文提出了一种用于下一代深亚微米低压CMOS闪存a /D转换器(ADC)的新型电压比较器——量子电压比较器。与传统的差分电压比较器不同,QV比较器的设计目的是尽量减少由于差分晶体管对不匹配而导致的输入偏置电压误差,QV比较器的设计目的是通过系统地、均匀地改变差分晶体管对的晶体管尺寸来优化输入偏置电压。QV比较器允许非常小的电压比较,完全消除电阻阶梯电路,并显着改善ADC的线性度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信