IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.最新文献

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Toward design technology in 2020: trends, issues, and challenges [VLSI design] 面向2020年的设计技术:趋势、问题和挑战[VLSI设计]
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183344
J. Harlow
{"title":"Toward design technology in 2020: trends, issues, and challenges [VLSI design]","authors":"J. Harlow","doi":"10.1109/ISVLSI.2003.1183344","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183344","url":null,"abstract":"VLSI design does not stand alone. The challenges and opportunities for the design community are driven and shaped by larger forces, from semiconductor technology evolution through product trends, and ultimately to large scale societal forces which are far beyond the control of designers. To understand the requirements for design, then, we first need to examine the larger environment in which we operate. Predictions are notoriously inaccurate, but I attempt to outline the global issues and technological trends that shape what designers must do. In my presentation, I risk some prognostications about the specific trends and challenges in the VLSI design field over the next 20 years, in hope that I retire long before anyone thinks to check my predictions.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117210084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Energy recovering ASIC design 能量回收ASIC设计
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183364
C. Ziesler, Joohee Kim, M. Papaefthymiou
{"title":"Energy recovering ASIC design","authors":"C. Ziesler, Joohee Kim, M. Papaefthymiou","doi":"10.1109/ISVLSI.2003.1183364","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183364","url":null,"abstract":"Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering most of this energy by using a novel energy recovering flip-flop and a novel single-phase resonant clock generator. As our state element has near-zero energy consumption when the input data is not switching, it provides the savings of clock gating approaches without the additional complexity of implementing clock gating in the design. To complement this near-zero idle energy property of the flip-flop, our resonant clock generator includes the capability to decide, on a per-cycle basis, whether or not the resonant clock needs to be replenished on the next cycle, thus automatically reducing energy consumption when most of the state elements are idling. ASICs designed with our methodology can achieve sub-C/spl middot/V/sub dd//sup 2/ dissipations on the clock network at frequencies of 200-500MHz and operating voltages of 1.0-1.5V in a 0.25 /spl mu/m process. To evaluate our methodology, we simulated a dual-mode (conventional and energy recovering) ASIC module to directly compare energy savings between the energy recovering and conventional clocking schemes. Our simulations demonstrate savings of over a factor of 4 for the energy-recovering mode versus the conventional mode for low switching activities.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124642337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Decoder-based multi-context interconnect architecture 基于解码器的多上下文互连架构
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183478
Andrea Lodi, L. Ciccarelli, A. Cappelli, F. Campi, M. Toma
{"title":"Decoder-based multi-context interconnect architecture","authors":"Andrea Lodi, L. Ciccarelli, A. Cappelli, F. Campi, M. Toma","doi":"10.1109/ISVLSI.2003.1183478","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183478","url":null,"abstract":"Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. To overcome this limitation a new decoder-based interconnect architecture is proposed. Dramatic improvements in terms of area and delay with respect to previous approaches are presented, such that multi-context FPGAs can finally become a viable solution for next generation configurable devices.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Energy benefits of a configurable line size cache for embedded systems 嵌入式系统的可配置行大小缓存的能源效益
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183357
Chuanjun Zhang, F. Vahid, W. Najjar
{"title":"Energy benefits of a configurable line size cache for embedded systems","authors":"Chuanjun Zhang, F. Vahid, W. Najjar","doi":"10.1109/ISVLSI.2003.1183357","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183357","url":null,"abstract":"Previous work has shown that cache line sizes impact performance differently for different desktop programs; some programs work better with small line sizes, others with larger line sizes. Typical processors come with a line size that is a compromise, working best on the average for a variety of programs. We analyze the energy impact of different line sizes, for 19 embedded system benchmarks, and we show that tuning the line size to a particular program can reduce memory access energy by 50% in some examples. Our data argues strongly for the need for embedded microprocessors to have configurable line size caches, and for embedded system designers to put effort into choosing the best line size for their programs.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129479275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Three-dimensional integrated circuits: performance, design methodology, and CAD tools 三维集成电路:性能、设计方法和CAD工具
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183348
Shamik Das, A. Chandrakasan, R. Reif
{"title":"Three-dimensional integrated circuits: performance, design methodology, and CAD tools","authors":"Shamik Das, A. Chandrakasan, R. Reif","doi":"10.1109/ISVLSI.2003.1183348","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183348","url":null,"abstract":"Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active devices together with high-density local interconnects between these layers, 3-D technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated. In this paper, we quantify the benefits 3-D integration can provide, using specific circuit benchmarks. We perform this analysis using a suite of circuit design tools we have developed for 3-D integration. We observe that on average, 28% to 51% reduction in total wire length is possible over two to five wafers respectively; similarly, 31% to 56% reduction in the length of the longest wire is achievable. We also characterize the impact of technology parameters on these reductions.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121622574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
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