IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.最新文献_第5页

Pre-computation of rotation bits in unidirectional CORDIC for trigonometric and hyperbolic computations 用于三角和双曲计算的单向CORDIC旋转位的预计算

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183472

S. Ravichandran, V. Asari

引用次数: 3

Code compression techniques for embedded systems and their effectiveness 嵌入式系统的代码压缩技术及其有效性

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183492

Krishnan Sundaresan, N. Mahapatra

引用次数: 8

Frequency domain approach for CMOS ultra-wideband radios CMOS超宽带无线电的频域方法

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183481

Hyung-Jin Lee, D. Ha

引用次数: 11

Behavioral simulation of power line noise coupling in mixed-signal systems using SystemC 混合信号系统中电力线噪声耦合行为仿真

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183498

J. Lundgren, B. Oelmann, T. Ytterdal, P. Eriksson, M. Abdalla, M. O’nils

引用次数: 3

Interconnect effort - a unification of repeater insertion and logical effort 互连工作-中继器插入和逻辑工作的统一

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183353

Srividya Srinivasaraghavan, W. Burleson

{"title":"Interconnect effort - a unification of repeater insertion and logical effort","authors":"Srividya Srinivasaraghavan, W. Burleson","doi":"10.1109/ISVLSI.2003.1183353","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183353","url":null,"abstract":"Interconnects are assuming increasing importance in deep submicron design, however there is a significant gap between industrial design practice and classical results of uniform repeater insertion. This work questions two of the standard assumptions of academic interconnect circuits: 1) the uniformity of repeater sizes and spacing and 2) the boundary between logic and interconnects. This research explores the co-design of logic sizing and repeater insertion for improved delay, power and placement. The technique of logical effort is used to develop the sizing scheme for the logic including polarity considerations. Non-uniform repeater insertion is used to combine cascaded sizing and distributed wire buffering. HSPICE simulations carried out for the 0.18/spl mu/ technology show that combining the sized logic with uniform repeaters is faster than using minimum sized logic circuitry by about 10% while with non-uniform repeaters the gain is about 15%. The average power consumption of non-uniform repeater insertion is less than that of uniform insertion by about 20%. Non-uniform repeater insertion is also less placement sensitive (shifting the position of each repeater in the setup by about 40% results in a delay loss of only about 3% while for uniform repeaters the delay loss is about 20%).","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Dual threshold voltage circuits in the presence of resistive interconnects 存在电阻互连的双阈值电压电路

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183477

P. Larsson-Edefors, D. Eckerbert, H. Eriksson, L. Svensson

引用次数: 3

Hardware implementation of data compression algorithms for memory energy optimization 存储能量优化数据压缩算法的硬件实现

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183487

L. Benini, D. Bruni, A. Macii, E. Macii

引用次数: 5

Equalizing filter design for crosstalk cancellation 用于串音消除的均衡滤波器设计

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183496

Jihong Ren, M. Greenstreet

引用次数: 2

Modified Sakurai-Newton current model and its applications to CMOS digital circuit design 修正的樱牛顿电流模型及其在CMOS数字电路设计中的应用

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183354

M. Mansour, M. M. Mansour, A. Mehrotra

{"title":"Modified Sakurai-Newton current model and its applications to CMOS digital circuit design","authors":"M. Mansour, M. M. Mansour, A. Mehrotra","doi":"10.1109/ISVLSI.2003.1183354","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183354","url":null,"abstract":"This paper presents a model for estimating the drain current in deep submicron CMOS devices. The model presented is an extension of Sakurai and Newton's model (SN-model), and hence is referred to as the modified SN-model (MSN-model). The proposed model preserves the simplicity of the SN-model while providing accurate drain current estimates for varying device widths. The transistor drain current values predicted by the proposed model are compared with HSPICE level 49 simulations for 0.25 /spl mu/m and 0.18 /spl mu/m CMOS processes. Manually computed current values for inverter circuits via the proposed model match HSPICE simulations on average to within 1.2% (3% maximum) over a wide range of transistor widths, fanouts, and input rise/fall times. Further this model is accurate in estimating the current in series-connected transistors having arbitrary widths, where the previous SN-model requires a delay degradation factor with transistors of equal sizes in order to work. The proposed model has been successfully incorporated into a senior level circuit design course at the University of Illinois at Urbana-Champaign.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115169404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Dynamic coding technique for low-power data bus 低功耗数据总线的动态编码技术

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183488

M. Madhu, V. Murty, V. Kamakoti

引用次数: 30