Dual threshold voltage circuits in the presence of resistive interconnects

Abstract

We consider the power-optimal design of dual-V/sub T/ CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V/sub T/ and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.