存在电阻互连的双阈值电压电路

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI:10.1109/ISVLSI.2003.1183477

P. Larsson-Edefors, D. Eckerbert, H. Eriksson, L. Svensson

{"title":"存在电阻互连的双阈值电压电路","authors":"P. Larsson-Edefors, D. Eckerbert, H. Eriksson, L. Svensson","doi":"10.1109/ISVLSI.2003.1183477","DOIUrl":null,"url":null,"abstract":"We consider the power-optimal design of dual-V/sub T/ CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V/sub T/ and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Dual threshold voltage circuits in the presence of resistive interconnects\",\"authors\":\"P. Larsson-Edefors, D. Eckerbert, H. Eriksson, L. Svensson\",\"doi\":\"10.1109/ISVLSI.2003.1183477\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We consider the power-optimal design of dual-V/sub T/ CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V/sub T/ and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183477\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183477","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

我们考虑在具有挑战性的延迟约束下，以阈值电压和器件尺寸为设计变量的双v /sub T/ CMOS电路的功率优化设计。我们表明，互连电阻的存在会影响V/sub / T/和器件尺寸的最佳选择，并且忽略电阻会导致高度次优的结果。我们还提出了决定何时应考虑互连电阻的标准。

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Dual threshold voltage circuits in the presence of resistive interconnects

We consider the power-optimal design of dual-V/sub T/ CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V/sub T/ and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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