{"title":"嵌入式系统的代码压缩技术及其有效性","authors":"Krishnan Sundaresan, N. Mahapatra","doi":"10.1109/ISVLSI.2003.1183492","DOIUrl":null,"url":null,"abstract":"Code compression techniques have been used widely in embedded systems to decrease the amount of storage resources needed or to decrease power consumption, and in some cases, to improve performance too. This paper evaluates, using cache models, the performance, power and cost benefits that code compression can provide in an instruction memory hierarchy. It also compares several important code compression schemes on a common platform and using a common set of benchmarks to gauge their effectiveness.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Code compression techniques for embedded systems and their effectiveness\",\"authors\":\"Krishnan Sundaresan, N. Mahapatra\",\"doi\":\"10.1109/ISVLSI.2003.1183492\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Code compression techniques have been used widely in embedded systems to decrease the amount of storage resources needed or to decrease power consumption, and in some cases, to improve performance too. This paper evaluates, using cache models, the performance, power and cost benefits that code compression can provide in an instruction memory hierarchy. It also compares several important code compression schemes on a common platform and using a common set of benchmarks to gauge their effectiveness.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183492\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Code compression techniques for embedded systems and their effectiveness
Code compression techniques have been used widely in embedded systems to decrease the amount of storage resources needed or to decrease power consumption, and in some cases, to improve performance too. This paper evaluates, using cache models, the performance, power and cost benefits that code compression can provide in an instruction memory hierarchy. It also compares several important code compression schemes on a common platform and using a common set of benchmarks to gauge their effectiveness.