Dynamic coding technique for low-power data bus

Abstract

Designing chips for lower power applications is one of the most important challenges faced by the VLSI designers. Since the power consumed by I/O pins of a CPU is a significant source of power consumption, work has been done on developing encoding schemes for reducing switching activity on external buses. In this paper we propose a new coding technique, namely, the Dynamic Coding Scheme, for low-power data bus. Our method considers two logical groupings of the bus lines, each being a permutation of the bus lines, and dynamically selects that grouping which yields the minimum number of transitions.