Modified Sakurai-Newton current model and its applications to CMOS digital circuit design

Abstract

This paper presents a model for estimating the drain current in deep submicron CMOS devices. The model presented is an extension of Sakurai and Newton's model (SN-model), and hence is referred to as the modified SN-model (MSN-model). The proposed model preserves the simplicity of the SN-model while providing accurate drain current estimates for varying device widths. The transistor drain current values predicted by the proposed model are compared with HSPICE level 49 simulations for 0.25 /spl mu/m and 0.18 /spl mu/m CMOS processes. Manually computed current values for inverter circuits via the proposed model match HSPICE simulations on average to within 1.2% (3% maximum) over a wide range of transistor widths, fanouts, and input rise/fall times. Further this model is accurate in estimating the current in series-connected transistors having arbitrary widths, where the previous SN-model requires a delay degradation factor with transistors of equal sizes in order to work. The proposed model has been successfully incorporated into a senior level circuit design course at the University of Illinois at Urbana-Champaign.