IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.最新文献_第4页

LALM: a logic-aware layout methodology to enhance the noise immunity of domino circuits LALM:一种提高多米诺电路抗噪能力的逻辑感知布局方法

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183352

Yonghee Im, K. Roy

引用次数: 1

Reconfigurable fast memory management system design for application specific processors 可重构快速内存管理系统设计的应用程序特定的处理器

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183358

S. K. Agun, J. M. Chang

引用次数: 6

Using dynamic branch behavior for power-efficient instruction fetch 使用动态分支行为实现高效的指令获取

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183363

Jie S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir

{"title":"Using dynamic branch behavior for power-efficient instruction fetch","authors":"Jie S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir","doi":"10.1109/ISVLSI.2003.1183363","DOIUrl":"https://doi.org/10.1109/ISVLSI.2003.1183363","url":null,"abstract":"Power consumption has become an increasing concern in high performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instruction cache contributes a large portion of the total power consumption in the microprocessor The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flows to boost performance, conventional trace caches (CTC) may increase power consumption in the fetch unit due to its simultaneous access to both the trace cache and the instruction cache. By avoiding this simultaneous accesses, sequential trace caches (STC) achieve lower power consumption, but suffer a significant performance loss at the meantime. In this paper we propose dynamic direction prediction based trace cache (DPTC) which avoids simultaneous accesses to the trace cache and the instruction cache with the guide of fetch direction prediction. Experimental results show that dynamic prediction based trace cache can achieve 38.5% power reduction over conventional trace caches and an additional 7.2% reduction over STC, on average, while only trading a 1.8% performance loss compared to CTC.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123381571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Q-Tree: a new iterative improvement approach for buffered interconnect optimization q树:一种新的迭代改进的缓冲互连优化方法

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183444

A. Kahng, Bao Liu

引用次数: 19

Networks-on-chip: the quest for on-chip fault-tolerant communication 片上网络:对片上容错通信的探索

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183347

R. Marculescu

引用次数: 66

Testable sequential circuit design: partitioning for pseudoexhaustive test 可测试顺序电路设计:伪穷举测试分区

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183484

B. Shaer, K. Aurangabadkar, N. Agarwal

引用次数: 3

An area-efficient Euclidean algorithm block for Reed-Solomon decoder 一种面积高效的里德-所罗门解码器欧几里得算法块

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183468

Hanho Lee

引用次数: 37

Block-wise extraction of Rent's exponents for an extensible processor 为可扩展处理器提取Rent的指数块

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183463

T. Ahonen, T. Nurmi, J. Nurmi, J. Isoaho

引用次数: 10

An O(N) supply voltage assignment algorithm for low-energy serially connected CMOS modules and a heuristic extension to acyclic data flow graphs 低功耗串联CMOS模块的O(N)电源电压分配算法及对无环数据流图的启发式扩展

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183443

A. U. Diril, Y. S. Dhillon, Kyu-won Choi, A. Chatterjee

引用次数: 6

High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders 基于细粒度流水线乘法器和加法器的高通量功率感知FIR滤波器设计

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI: 10.1109/ISVLSI.2003.1183490

J. Di, Jiann-Shiun Yuan, R. Demara

引用次数: 31