可测试顺序电路设计:伪穷举测试分区

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI:10.1109/ISVLSI.2003.1183484

B. Shaer, K. Aurangabadkar, N. Agarwal

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引用次数: 3

摘要

在这项研究中，我们提出了一种自动算法，该算法将大型顺序VLSI电路划分为伪穷举测试。划分算法基于电路中各节点的主输入锥和扇出值。我们开发了一个优化过程，可用于找到主输入锥和扇出值的最佳尺寸，用于划分给定电路。实验结果证明了我们工作的有效性。

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Testable sequential circuit design: partitioning for pseudoexhaustive test

In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work.

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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