Testable sequential circuit design: partitioning for pseudoexhaustive test

Abstract

In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work.