{"title":"用于0.07 /spl mu/m CMOS闪存A/D转换器的量子电压比较器","authors":"Jincheol Yoo, Kyusun Choi, J. Ghaznavi","doi":"10.1109/ISVLSI.2003.1183500","DOIUrl":null,"url":null,"abstract":"This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters\",\"authors\":\"Jincheol Yoo, Kyusun Choi, J. Ghaznavi\",\"doi\":\"10.1109/ISVLSI.2003.1183500\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183500\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters
This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.