缩小PD-SOI CMOS浮体效应的新型电路

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI:10.1109/ISVLSI.2003.1183350

K. Das, Richard B. Brown

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引用次数: 3

摘要

SOI(绝缘体上硅)技术受到许多浮体效应的影响，最明显的是寄生双极效应和历史效应。这些都受到超薄栅极氧化物引起的快速增加的栅极隧道电流的影响，即使在一定比例的V/sub DD/s下也是如此。本文详细分析了这些影响，并提出了一些新颖的电路样式来最小化这些影响。仿真结果基于AMD 0.25 /spl mu/m PD-SOI工艺的模型参数。

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Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled V/sub DD/s. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 /spl mu/m PD-SOI process.

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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