{"title":"一种有效的D/A变换器系统电流失配校正技术","authors":"K. Baek, M. Choe, S. Kang","doi":"10.1109/ISVLSI.2003.1183356","DOIUrl":null,"url":null,"abstract":"This paper presents a current calibration technique for systematic mismatch in current-cell array. The proposed technique is suitable for GHz-range current-steering D/A converters because of an efficient and totally independent calibration operation. Behavioral simulation and measurement results show that static and yield performance of a D/A converter can be enhanced significantly by using the proposed technique. A measured reduction in INL and DNL errors before and after calibration is from +33.2/-60.1 LSB to +1.28/-1.28 LSB and from +10.2/-12.8 LSB to +2.56/-1.28 LSB in 12-bit resolution.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An efficient calibration technique for systematic current-mismatch of D/A converters\",\"authors\":\"K. Baek, M. Choe, S. Kang\",\"doi\":\"10.1109/ISVLSI.2003.1183356\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a current calibration technique for systematic mismatch in current-cell array. The proposed technique is suitable for GHz-range current-steering D/A converters because of an efficient and totally independent calibration operation. Behavioral simulation and measurement results show that static and yield performance of a D/A converter can be enhanced significantly by using the proposed technique. A measured reduction in INL and DNL errors before and after calibration is from +33.2/-60.1 LSB to +1.28/-1.28 LSB and from +10.2/-12.8 LSB to +2.56/-1.28 LSB in 12-bit resolution.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183356\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183356","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient calibration technique for systematic current-mismatch of D/A converters
This paper presents a current calibration technique for systematic mismatch in current-cell array. The proposed technique is suitable for GHz-range current-steering D/A converters because of an efficient and totally independent calibration operation. Behavioral simulation and measurement results show that static and yield performance of a D/A converter can be enhanced significantly by using the proposed technique. A measured reduction in INL and DNL errors before and after calibration is from +33.2/-60.1 LSB to +1.28/-1.28 LSB and from +10.2/-12.8 LSB to +2.56/-1.28 LSB in 12-bit resolution.
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