{"title":"Supply and demand for high temperature electronics","authors":"S. Lande","doi":"10.1109/HITEN.1999.827477","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827477","url":null,"abstract":"The driving force for components capable of high temperature operation is the elimination of expensive and bulky cooling systems which are currently required to protect electronics from extreme environments. This would result in improved system architectures, increased performance and efficiency, reduced environmental emissions, and large cost-savings. The authors discuss applications of high temperature electronics to well logging and the aerospace and automotive industries.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120994577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DCB substrates: solution for high temperature applications","authors":"J. Schulz-Harder","doi":"10.1109/HITEN.1999.827465","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827465","url":null,"abstract":"Summary form only given. DBC (Direct Bonded Copper) substrates have been proved over many years to be the most cost effective and reliable solution for circuits in power electronics. The bases of these substrates are ceramics, either alumina or aluminium nitride. The metallisation consists of copper layers bonded to ceramic at high temperature. DBC differs from thick film metallisation in that the copper layers consist of pure metal with high electric conductivity whereas the DBC process is carried out at temperatures above 1065/spl deg/C; the working temperature of DBC substrates can be up to 900/spl deg/C. DBC substrates are successfully brazed to covar at temperatures of 850/spl deg/C to 900/spl deg/C without affecting their functionality. At temperatures above 500/spl deg/C in hydrogen atmosphere the copper/ceramic interface peel strength is reduced. The copper surface of DBC substrates can be protected against oxidation by plating (Ni+Au) as a standard process. The range thickness of DCB is between 0.2 and 0.7 mm. Standard thicknesses are 0.2 mm and 0.3 mm. The reliability of DBC substrate temperature cycling is dependent on the absolute temperature and the temperature range. For military and automotive specifications the reliability could be improved by reducing the copper thickness at the copper edges by a simple low cost etching process.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability physics and electronics design for high operating temperatures","authors":"B. Peat","doi":"10.1109/HITEN.1999.827476","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827476","url":null,"abstract":"The collection of slides from the author's conference presentation is provided.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Temperature dependence of avalanche breakdown in GaAs p-i-n diodes","authors":"J. David, R. Ghin, S.A. Plimmer, G. Rees, R. Grey","doi":"10.1109/HITEN.1999.827492","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827492","url":null,"abstract":"We investigate the changes to the avalanche multiplication and breakdown voltage in a series of epitaxially grown GaAs p-i-n diodes with nominal intrinsic region thicknesses of 1/spl mu/m, 0.5/spl mu/m and O.1/spl mu/m, over the temperature range 20K-500K.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Demeus, P. Delatte, V. Dessard, S. Adriaensen, A. Viviani, C. Renaux, D. Flandre
{"title":"The art of high temperature FD-SOI CMOS","authors":"L. Demeus, P. Delatte, V. Dessard, S. Adriaensen, A. Viviani, C. Renaux, D. Flandre","doi":"10.1109/HITEN.1999.827472","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827472","url":null,"abstract":"This paper presents the latest results of our research on SOI (Silicon-On-Insulator) technology for high temperature electronics. We focus on Fully-Depleted SOI (FD-SOI) because it achieves superior high temperature results compared with Partially Depleted (PD-SOI) technology. Our interest includes both technology considerations and circuit studies. We show that FD-SOI is an efficient way to implement high performance circuits for high temperature applications. Some essential aspects for the development of reliable high temperature SOI analog circuits are addressed: lifetime, voltage reference, noise and basic analog building blocks. We discuss some technological characteristics of our SOI process, then focus on lateral bipolar transistors (FD-SOI-CMOS Compatible) which are necessary for good bandgap references, compare noise performance in FD and PD SOI technologies, and finally present some of our latest results relating to critical analog building blocks for high temperature electronics.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132976224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Rudenko, V. Lysenko, A. Rudenko, V. Kilchytska, J. Colinge
{"title":"A study on the high-temperature subthreshold slope in SOI MOSFETs","authors":"T. Rudenko, V. Lysenko, A. Rudenko, V. Kilchytska, J. Colinge","doi":"10.1109/HITEN.1999.827462","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827462","url":null,"abstract":"In this paper, the validity of a classical expression for the subthreshold swing in SOI MOSFETs is revised for high-temperature conditions. Using numerical simulation, it is demonstrated that at high temperatures (above 150/spl deg/C) the depletion approximation is no longer valid, and the free carriers must be taken into account in the determination of the effective substrate capacitance. Another correction must be introduced into the classical expression to account for the inversion layer broadening caused by lowering the surface electric field in a weak inversion region with temperature.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. McCluskey, R. Jain, N. Tiwari, R. Grzybowski, J. Benoit, S. Lin
{"title":"Die attach and wirebond systems for high temperature electronics","authors":"F. McCluskey, R. Jain, N. Tiwari, R. Grzybowski, J. Benoit, S. Lin","doi":"10.1109/HITEN.1999.827464","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827464","url":null,"abstract":"Summary form only given. Creating a reliable electronic system that can operate at temperatures in excess of 200/spl deg/C requires more than just developing ICs that can function at these temperatures. It also requires developing packaging technologies that can accommodate device operation. Three critical packaging related failure mechanisms in components and modules at high temperatures are intermetallic formation at the wire bonds, wire annealing at the midspan, and die attach fatigue at the die to substrate interface. This paper will describe the relative reliability of various die attach materials and wirebonding systems proposed for high temperature electronics. Results of die shear, bond shear, and wire pull strength measurements on die attach and wirebond materials, respectively, after aging for 1000 hours at 260/spl deg/C and after temperature cycling from -55/spl deg/C to 260/spl deg/C for 1000 cycles will be presented. These results will be analyzed using a new viscoplastic shear stress and damage model for die attach fatigue and a new model for wire annealing which can be used to assess the susceptibility of high temperature electronic modules to failure by these mechanisms.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123115158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Kalinina, A. Zubrilov, A. Strel'chuk, V. A. Solov'ev, V. Dmitriev
{"title":"Electrical and optical properties of Mg ion implanted GaN p-n junctions","authors":"E. Kalinina, A. Zubrilov, A. Strel'chuk, V. A. Solov'ev, V. Dmitriev","doi":"10.1109/HITEN.1999.827470","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827470","url":null,"abstract":"In this paper we report the electrical and optical properties of GaN p-n diodes fabricated by Mg ion implantation doping of n-type GaN epitaxial layers. Ion implantation was performed at room temperature with doses ranged from 10/sup 13/ to 2/spl times/10/sup 16/ cm/sup -2/. After implantation samples were annealed for 10-15 s at a wide temperature interval from 600/spl deg/C to 1200/spl deg/C in flowing N/sub 2/ to form p-type layers. Scanning electron microscopy with electron beam induced current and back scattered electron modes as well as current-voltage and capacitance-voltage measurements were used to study structural and electrical characteristics of the Mg implanted p-n structures. Samples were characterized by photoluminescence. Electroluminescence from Mg implanted p-n junction structures has been observed for the first time.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113968387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Strel'chuk, V. Kozlovski, N. Smirnova, J.J.P. Pil'kevich, M. Rastegaeva
{"title":"Effect of irradiation on excess currents in 6H-SiC p-n structures","authors":"A. Strel'chuk, V. Kozlovski, N. Smirnova, J.J.P. Pil'kevich, M. Rastegaeva","doi":"10.1109/HITEN.1999.827474","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827474","url":null,"abstract":"Summary form only given. The results of investigations of the influence exerted by different kinds of irradiation of SiC p-n structures on the magnitude of forward and reverse excess currents are presented. The objects of study were 6H-SiC p/sup +/-n structures based on commercial n and p epitaxial layers.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115878804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Matched expansion probe cards","authors":"E. Ehlermann","doi":"10.1109/HITEN.1999.827490","DOIUrl":"https://doi.org/10.1109/HITEN.1999.827490","url":null,"abstract":"Summary form only given. When testing IC's on a wafer prober a standard state of the art probe card will show a dislocation of the probe needles relative to the pad positions at elevated temperature. By separating electrical and mechanical features it is possible to have matched expansion while the actual electrical adaption of the user remains unmodified. The Matched Expansion Probe Card offers this feature for application over a range of temperatures which may be offset more than +/-200/spl deg/C from the temperature of manufacturing. The only limitations of this solution are the stability of the embedment and the liquidus temperature of the solder used. By this method the manufacturer and the maintenance group can save the need of using a hotchuck and protecting gloves. The application is field proven up to 135/spl deg/C and is actually field tested at 185/spl deg/C. Temperatures above 250/spl deg/C for electro-migration measurements have been performed in a laboratory environment.","PeriodicalId":297771,"journal":{"name":"HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)","volume":"45 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129701393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}