Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)最新文献_第3页

High reliable solder joints using Sn-Pb-La solder alloy 采用Sn-Pb-La焊料合金的高可靠焊点

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941456

X. Ma, Y. Qian, F. Liu, F. Yoshida

引用次数: 2

Application of focused ion beam system as a defect localization and root cause analysis tool 聚焦离子束系统作为缺陷定位和根本原因分析工具的应用

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941466

C. C. Ooi, K. H. Siek, K. Sim

引用次数: 2

Failure analysis challenges 故障分析挑战

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941451

Larry Wagner

{"title":"Failure analysis challenges","authors":"Larry Wagner","doi":"10.1109/IPFA.2001.941451","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941451","url":null,"abstract":"Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115538146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Thermo-mechanical analysis for a multi chip build up substrate based package 基于多芯片构建基板封装的热力学分析

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941457

Xiaowu Zhang, C. Lee, W. Hua, M. Iyer, Teo Poi Siong, D. Pinjala, S. Srinivasamurthy

{"title":"Thermo-mechanical analysis for a multi chip build up substrate based package","authors":"Xiaowu Zhang, C. Lee, W. Hua, M. Iyer, Teo Poi Siong, D. Pinjala, S. Srinivasamurthy","doi":"10.1109/IPFA.2001.941457","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941457","url":null,"abstract":"This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the 2nd level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. Firstly, the effect of the positioning of four silicon dice within the MCM package on the package warpage was studied. Secondly, the effect of package dimensions (the heat spreader thickness, structural adhesive thickness and substrate thickness) on the maximum residual stress and warpage of the package were performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of the solder joints is estimated by Darveaux's approach. A series of parametric studies is performed by changing the package dimensions. The results obtained from the modeling are useful for the design of multichip packages.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127102895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

New methods for scanning ultrasonic microscopy applications for failure analysis of microassembling technologies 扫描超声显微镜应用于微装配技术失效分析的新方法

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941485

L. Béchou, Y. Ousten, Y. Danto

引用次数: 9

Bipolar current stressing and electrical recovery of quasi-breakdown in thin gate oxides 薄栅氧化物准击穿的双极电流应力和电恢复

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941455

W. Loh, B. Cho, M. Li

引用次数: 0

ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration ESD植入在0.18-/spl mu/m的盐化CMOS技术中进行片上ESD保护，并考虑布局

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941461

M. Ker, Che-Hao Chuang

引用次数: 23

Borderless contact leakage induced standby current failure on sub-0.15 /spl mu/m CMOS device 在低于0.15 /spl mu/m的CMOS器件上无边界触点漏电引起待机电流失效

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941478

D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S.B. Kim, J. Hong, J. Park, M.Y. Lee

引用次数: 2

Emitter base junction ESD reliability of an epitaxial base silicon germanium heterojunction bipolar transistor 外延基硅锗异质结双极晶体管发射极结ESD可靠性研究

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941460

S. Voldman, L. Lanzerotti, R. Johnson

引用次数: 15

Short failure analysis under fault isolation 故障隔离下的短故障分析

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941486

Z. Mai, M. Palaniappan, J. Chin, C. E. Soh, L.A. Knauss, E. Fleet

引用次数: 4