Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)最新文献_第5页

Direction of silicon technology from past to future 硅技术从过去到未来的发展方向

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941450

H. Iwai

引用次数: 6

Failure analysis from the back side of a die 从模具背面进行失效分析

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941484

S. Liebert

{"title":"Failure analysis from the back side of a die","authors":"S. Liebert","doi":"10.1109/IPFA.2001.941484","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941484","url":null,"abstract":"Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125827512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Effect of transmission line pulsing of interconnects investigated using combined low-frequency noise and resistance measurements 采用低频噪声和电阻测量相结合的方法研究了传输线脉冲对互连的影响

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941463

L. W. Chu, W. Chim, K. Pey, A. See

引用次数: 2

Impact of ESD-induced soft drain junction damage on CMOS product lifetime 静电致软漏极损伤对CMOS产品寿命的影响

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2000-08-01 DOI: 10.1109/IPFA.2001.941459

J. Reiner, T. Keller, H. Jaggi, S. Mira

引用次数: 9

Generation of hole traps in silicon dioxides 二氧化硅中空穴阱的产生

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 1900-01-01 DOI: 10.1109/IPFA.2001.941453

J.F. Zhang, H. K. Sii, G. Groeseneken, R. Degraeve

引用次数: 2

Investigation of hot-carrier induced interface damages via small-signal characteristics of drain-to-substrate gated-diode 基于漏极-衬底栅极二极管小信号特性的热载子界面损伤研究

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 1900-01-01 DOI: 10.1109/IPFA.2001.941496

M. Lau, C.T. Hsu, Y. Yeow

{"title":"Investigation of hot-carrier induced interface damages via small-signal characteristics of drain-to-substrate gated-diode","authors":"M. Lau, C.T. Hsu, Y. Yeow","doi":"10.1109/IPFA.2001.941496","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941496","url":null,"abstract":"The DC gated-diode current measurement has been used extensively to study hot-carrier induced degradation in MOSFETs. This technique relies on the property of interface states acting as effective recombination centres to detect their presence. According to Shockley-Read-Hall recombination theory (Muller and Kamins, 1986), gated-diode generation/recombination current is mainly contributed by states close to the midgap. This paper presents a study of the small-signal characteristics of the drain-to-substrate junction of an n-channel MOSFET configured as a gated diode to study hot-carrier induced degradation. This small-signal admittance consists of the small-signal drain-to-substrate capacitance and conductance (C/sub db/ and G/sub db/). Similar to DC gated diode characterisation, the small signal admittance uses the change in the space charge region of the gated-diode to detect the presence and the spatial distribution of hot-carrier induced interface and trapped charges. G/sub db/ is sensitive to change in midgap interface states acting as recombination centres as well as any change in bulk recombination due to change in the volume of the spatial charge region. It corresponds to the slope of the DC diode I-V characteristics of the junction. Change in C/sub db/ reflects the width of the diode space charge region. Therefore, the information obtained from the analysis of C/sub db/ and G/sub db/ before and after electrical stressing are complementary to each other. We compare experimental results for C/sub db/ and G/sub db/ to show the applicability of this method to characterize hot carrier stress response of submicron MOSFETs.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

High resistance via induced by marginal barrier metal step coverage and F diffusion 由于边缘障碍金属台阶覆盖和F扩散引起的高电阻

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 1900-01-01 DOI: 10.1109/IPFA.2001.941482

J. Y. Dai, S. K. Loh, S. F. Tee, C. L. Tay, S. Ansari, E. Er, S. Redkar

{"title":"High resistance via induced by marginal barrier metal step coverage and F diffusion","authors":"J. Y. Dai, S. K. Loh, S. F. Tee, C. L. Tay, S. Ansari, E. Er, S. Redkar","doi":"10.1109/IPFA.2001.941482","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941482","url":null,"abstract":"In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process 1.8 v 0.15-/spl mu/m部分耗尽SOI盐化CMOS工艺中的新型二极管结构和ESD保护电路

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 1900-01-01 DOI: 10.1109/IPFA.2001.941462

M. Ker, Kei-Kang Hung, H. Tang, S. Huang, S.-S. Chen, M. Wang

引用次数: 14