M. Ker, Kei-Kang Hung, H. Tang, S. Huang, S.-S. Chen, M. Wang
{"title":"Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process","authors":"M. Ker, Kei-Kang Hung, H. Tang, S. Huang, S.-S. Chen, M. Wang","doi":"10.1109/IPFA.2001.941462","DOIUrl":null,"url":null,"abstract":"Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2001.941462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).
1.8 v 0.15-/spl mu/m部分耗尽SOI盐化CMOS工艺中的新型二极管结构和ESD保护电路
由于薄膜硅层下埋藏氧化物的低导热性和绝缘层上的浅沟隔离(STI)结构,在绝缘体上硅(SOI) CMOS技术中CMOS器件的静电放电(ESD)稳健性已成为主要的可靠性挑战(Chan et al., 1994;Raha et al., 1999;史密斯,1998)。随着SOI技术的不断缩小,顶层硅膜的厚度减小,用于ESD保护器件放电ESD电流的结面积变小。因此,SOI CMOS ic中由ESD事件产生的热量的散热能力严重下降。在部分耗尽SOI CMOS技术中,提出了两种具有更大p-n结面积的新型二极管结构,以获得更好的散热效果。对这些新型二极管的I-V特性和ESD稳健性进行了研究,并与Lubistor二极管进行了比较(Voldman et al., 1996)。