Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)最新文献_第4页

Characterization of Cu extrusion failure mode in dual-damascene Cu/low-k interconnects under electromigration reliability test 电迁移可靠性试验下双damascene Cu/low-k互连铜挤压失效模式表征

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941480

Jeung-Woo Kim, Won-sang Song, Sam-Young Kim, Hyan-Soo Kim, Hyungoo Jeon, Chae-Bog Lim

{"title":"Characterization of Cu extrusion failure mode in dual-damascene Cu/low-k interconnects under electromigration reliability test","authors":"Jeung-Woo Kim, Won-sang Song, Sam-Young Kim, Hyan-Soo Kim, Hyungoo Jeon, Chae-Bog Lim","doi":"10.1109/IPFA.2001.941480","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941480","url":null,"abstract":"With low electrical resistivity and superb electromigration properties relative to Al, Cu is considered an exemplary candidate for metallization in logic devices. The electromigration characteristics, however, are highly contingent upon the test criteria, which in turn vary with the test structure and/or materials, e.g. inter/intra-metal dielectrics. The thermal mismatch stress existing between low-k SiOF and Cu, for instance, degrades the metal adhesion and curtails the device lifetime (Riedel, 1997). Such deleterious stress may also induce an extrusion mode failure, resulting in an unstable EM data with high sigma (Ennis, 2000) and an improper estimation of via lifetime. In this study, we identify a few pertinent factors involved in the formation of Cu extrusion mode failures in a Cu-SiOF dual damascene structure, and propose a possible underlying mechanism. Extrusion-free specimens, i.e. once the problem is eliminated, show an activation energy of about 0.81 eV, and the EM failures are limited to the via regions.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Development and optimization of substrate failure analysis techniques for chip scale packages 芯片级封装衬底失效分析技术的发展与优化

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941458

L. B. Yew, C. Francis, S. Mohamed, Tang Wye Mun, L. Ki

引用次数: 1

Stress-induced leakage current in thin oxides under high-field impulse stressing 高场脉冲应力作用下薄氧化物的应力诱发泄漏电流

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941492

Y. Tan, W. Chim, P. Lim

引用次数: 1

Unique measurement to monitor the gate oxide lifetime indicator, case studies 独特的测量监测栅极氧化物寿命指标，案例研究

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941476

X. Gagnard, O. Bonnaud

引用次数: 1

The application of pattern correlation method between maps of failure bins and electrical parameters in fault isolation 故障仓图与电气参数模式相关法在故障隔离中的应用

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941487

Luo Ping, Neo Soh Ping

{"title":"The application of pattern correlation method between maps of failure bins and electrical parameters in fault isolation","authors":"Luo Ping, Neo Soh Ping","doi":"10.1109/IPFA.2001.941487","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941487","url":null,"abstract":"Normally, it is difficult to isolate and identify the root cause for sort failures, especially for functional failures. This problem is worst for the wafer foundry because of the limited information on the product from customer. Sort test failures are generally analysed by either a correlation study between yield and electrical test (ET) data on the ET structure in a scribe line or a fault isolation technique. The yield correlation method is not as efficient because of the complicated sort test, the limited electrical data (usually only a few sites for production wafers), and the variation of yield patterns and ET behaviour among wafers and lots. The fault isolation techniques may not be able to capture the failure defect, especially for functional failures. One of the major limitations for yield analysis is the irregular yield pattern and its variation among wafers and lots. An irregular yield pattern means a correspondingly similar irregular ET data pattern for those failure-related parameters. In other words, those failure-related ET parameters should have higher correlation with the yield map than the rest of parameters. Thus, based on the quantitative calculation of the correlation between the maps of failure bins and the ET parameters, those ET parameters with high correlation can be identified and reasonably believed to be failure-related. In this paper, the pattern correlation method is introduced and applied for a true case of functional failure with via issue.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A dry migration? Copper dendrite growth in adhesive tape during burn-in 干迁移?胶带灼烧过程中铜枝晶的生长

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941481

S. Tan, S. H. Ong

引用次数: 7

Modelling of the reservoir effect on electromigration lifetime 电迁移寿命的储层效应建模

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941479

H. Nguyen, C. Salm, T. Mouthaan, F. Kuper

{"title":"Modelling of the reservoir effect on electromigration lifetime","authors":"H. Nguyen, C. Salm, T. Mouthaan, F. Kuper","doi":"10.1109/IPFA.2001.941479","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941479","url":null,"abstract":"Electromigration behaviour in W-plug/metal stripe structures is different from conventional metal-strip structures because there is a blocking boundary formed by the immobile W-plug in the contact/via. Electromigration failures occur more readily close to the W-plug than in metal-strip structures because metal ions are forced away from the contacts/vias by electric current, blocking the contacts/vias area. Several works have reported electromigration lifetime of multiple level interconnects to be influenced by the presence of a reservoir around the contacts/vias. Reservoirs are metal parts that are not or are hardly conducting current that act as a source to provide atoms for the area around the blocking boundary where the atoms migrate away due to the electric current. Interconnect lifetime can be prolonged by using the reservoirs, called the \"reservoir effect\". 2D simulation of the effects of reservoirs has been performed. The stress build-up during electromigration in the contact area can be simulated for several configurations, separating the effects of overlap, total reservoir area, the reservoir layout directions (vertical and horizontal), number of contacts/vias and contact/via placement. It is very useful for IC design rules to estimate which parameters are important for IC reliability. In this study, we considered the critical stress that the metal line can sustain before void formation as failure criterion. The failure time is determined by the time to reach the critical stress.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129572898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Determination of BGA structural defects and solder joint defects by 3D X-ray laminography BGA结构缺陷和焊点缺陷的三维x射线层析测定

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941474

T. Moore, D. Vanderstraeten, P. Forssell

{"title":"Determination of BGA structural defects and solder joint defects by 3D X-ray laminography","authors":"T. Moore, D. Vanderstraeten, P. Forssell","doi":"10.1109/IPFA.2001.941474","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941474","url":null,"abstract":"The equipment and software for X-ray laminography has advanced rapidly in recent years. The latest systems can distinguish features as small as 5 /spl mu/m in diameter and identify their locations to within 10 /spl mu/m in three dimensions within an IC package. Details of complex closely spaced structures can be extracted readily with recently developed microlaminographs. At this resolution, the method is termed microlaminography. In this paper, the technology, methodology and results from a microlaminography system developed for failure analysis in IC packaging are presented. The copper traces in the built up layers of a BGA substrate were extracted and analysed individually. Bond-wire shorts in the plane of the solder resist in a lot of BGA assemblies were located and identified with subsequent verification by destructive physical analysis (DPA). 3D reconstructions of individual solder balls within an assembly were created and examined for defects. These analyses could not have been done by normal 2D X-ray; formerly only DPA could extract such information.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Elimination of opens failure between via holes and traces in LTCC multilayer substrate by coherent shrinkage 用相干收缩法消除LTCC多层衬底中通孔和迹线之间的开口失效

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941472

X. He, X. Ma, Y. Zhang

{"title":"Elimination of opens failure between via holes and traces in LTCC multilayer substrate by coherent shrinkage","authors":"X. He, X. Ma, Y. Zhang","doi":"10.1109/IPFA.2001.941472","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941472","url":null,"abstract":"MCM-C technology is based on the use of a multilayer ceramic substrate as the carrier for the various chip devices. Low temperature co-fired ceramic (LTCC), with the advantage of higher wiring density and lower dielectric constant, is widely used as the multilayer substrate for high density electronic packaging, such as MCM-C. The low firing temperature enables the use of precious metals in the conducting layers. With the development of MCM technology, the LTCC substrate is larger and has many more layers to satisfy the increasing assembly performance requirements. However, with the enlargement of substrate area, the firing shrinkage mismatch between the metal conductor and the ceramic matrix leads to the more serious problem of open failures (Imanaka et al., 1992; Miura et al., 1994; Itagaki et al., 1993). In this work, the open failure between via holes and traces in LTCC substrates was studied. The effect of compacting temperature, ceramic particle size, softening point, stack process and firing profile was reported. Finally, by means of coherent shrinkage, the open failure between via holes and traces in LTCC was eliminated effectively.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124468116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory 接触级离子束诱导无源电压对比在静态随机存储器失效分析中的应用

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) Pub Date : 2001-07-09 DOI: 10.1109/IPFA.2001.941464

Z.G. Song, G. Qian, J. Y. Dai, Z.R. Guo, S. K. Loh, C. Teh, S. Redkar

{"title":"Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory","authors":"Z.G. Song, G. Qian, J. Y. Dai, Z.R. Guo, S. K. Loh, C. Teh, S. Redkar","doi":"10.1109/IPFA.2001.941464","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941464","url":null,"abstract":"The demand for improvement of device speed and reduction of power consumption has driven semiconductor devices to be miniaturized continuously. To develop new process generations, static random access memory (SRAM) is often chosen as the process qualification vehicle because the quality and performance of SRAMs are direct reflections of high density and small feature size, and they are very sensitive to process variation. Therefore, analysis of SRAM failure is a critical time-to market path for process development. During sub-quarter micron process development, the integrity of high aspect ratio contacts was found to be a major concern. For contact defect analysis, focus ion beam (FIB) cross-sectioning is the best method. However, the problem remains of how to identify the defective contact. E-beam testing and optical beam-induced current (OBIC) techniques have been reported as tools for detecting defective contacts. However, few FA labs have such equipment. In this study, a novel technique of contact-level ion-beam induced passive voltage contrast was developed to identify defective contacts employing a FIB station, and its application was demonstrated by SRAM failure analysis.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11