Emitter base junction ESD reliability of an epitaxial base silicon germanium heterojunction bipolar transistor

Abstract

With the growth of the high-speed data rate transmission, optical interconnect, and wireless marketplaces, heterojunction devices will play a central role in these communication systems. Heterojunction base-emitter design, bandgap engineering and technology scaling will each play a key role in the ability to achieve faster devices for the wired and wireless markets. As these structures are scaled, the sensitivity of these devices to electrostatic overstress (EOS), electrostatic discharge (ESD) and electromagnetic emissions (EMI) becomes a concern. Emitter-base design influences the ESD sensitivity and device performance of heterojunction bipolar transistor (HBT) devices. In this paper, the ESD sensitivity of the emitter-base junction of a SiGe HBT device is discussed. The evaluation of process variations and device design spacings on ESD robustness is evaluated for both positive and negative stress conditions as a function of the salicide location, emitter-base spacing, and collector opening.