High resistance via induced by marginal barrier metal step coverage and F diffusion

Abstract

In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.