Borderless contact leakage induced standby current failure on sub-0.15 /spl mu/m CMOS device

D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S.B. Kim, J. Hong, J. Park, M.Y. Lee
{"title":"Borderless contact leakage induced standby current failure on sub-0.15 /spl mu/m CMOS device","authors":"D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S.B. Kim, J. Hong, J. Park, M.Y. Lee","doi":"10.1109/IPFA.2001.941478","DOIUrl":null,"url":null,"abstract":"For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 /spl mu/m CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 /spl mu/m 6-Tr SRAM device.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2001.941478","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 /spl mu/m CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 /spl mu/m 6-Tr SRAM device.
在低于0.15 /spl mu/m的CMOS器件上无边界触点漏电引起待机电流失效
对于具有高性能的CMOS器件设计规则的降尺度,减小的有源面积迫使在局部互连中形成无边界接触。随着接触面积的减小,器件的电气特性和可靠性将受到影响。作为低于0.15 /spl mu/m的CMOS器件基础技术的超浅结结构和沟槽浅边无边界接触漏电引起的结漏是低待机功耗CMOS器件面临的严重问题。最近,一些无边界接触结构被报道(Gallagher et al., 1995;Subbanna et al., 1993;刘文洲等,2000)。在本文中,我们估计了无边界触点的电气特性,并演示了在低于0.15 /spl mu/m的6-Tr SRAM器件上无边界触点泄漏引起的待机故障。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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