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Propagation of Terahertz Signal through Tropical Thunderstorm 太赫兹信号在热带雷暴中的传播
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032876
D. Chakraborty, M. Mukherjee
{"title":"Propagation of Terahertz Signal through Tropical Thunderstorm","authors":"D. Chakraborty, M. Mukherjee","doi":"10.1109/EDKCON56221.2022.10032876","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032876","url":null,"abstract":"The increasing demand of higher data rate as well as wider bandwidth, has enhanced the necessity to exploit Terahertz(THz) spectrum in upcoming wireless communication systems. Starting from non-ionization, several unique properties are present in this spectrum, for which THz signal analysis has already captured a major area of cutting-edge research in ultrafast communication systems. Atmospheric attenuation can be considered as the main drawback in free-space THz-signal communication. Different types of suspended and falling hydrometeors, present in the atmosphere, can lead to absorption and scattering of THz signal. Rain is the most common type of falling aerosol, that are categorized as drizzles, showers, thunderstorm etc., depending on their diameters and rate of precipitation. In tropical weather scenario, the propagation of THz signal can be seriously affected under atmospheric precipitation. The authors, for the first time, have indigenously developed a Non-Linear Terahertz Rain Attenuation Model(NLTRAM) to estimate the tropical Rain-Attenuation Spectra of free-space THz signal under varying rain-rate and varying drop-diameters. In tropical climatic condition, the effect of Raindrop Size Distribution(RSD) and Depth of THz(DoT) under varying rain-rates, has been thoroughly investigated as the preliminary part of this model simulation and presented in this paper.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121468379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Passive Lossless Snubber For the Boost Power Converters 升压电源变换器的无源无损缓冲器
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032829
T. Halder
{"title":"A Passive Lossless Snubber For the Boost Power Converters","authors":"T. Halder","doi":"10.1109/EDKCON56221.2022.10032829","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032829","url":null,"abstract":"In this paper, a simple lossless passive snubber cell is proposed for the boost converter to mitigate mainly turned off switching power losses of the main power MOSFET operated by turned off zero voltage switching (ZVS) operations with controller actions. The reverse recovery problems of the boost diode, switching transients and stresses across the main switch are reduced by the proposed snubber circuit which has enough potential for energy recovery or lossless operations to improve the performance of dc to dc Boost power converters","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121517040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Direct wafer-bonded two terminal GaAsP/Si dual junction solar cell with 19.80% efficiency 直接晶片键合双端GaAsP/Si双结太阳能电池，效率为19.80%
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032943
M. Verma, G. S. Sahoo, G. P. Mishra
{"title":"Direct wafer-bonded two terminal GaAsP/Si dual junction solar cell with 19.80% efficiency","authors":"M. Verma, G. S. Sahoo, G. P. Mishra","doi":"10.1109/EDKCON56221.2022.10032943","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032943","url":null,"abstract":"The low cost of Si material has enabled the design of III-V/Si based dual junction solar cell. The lattice mismatching between the two sub-cells leads to the Threading Dislocation density and poor current matching. In this work, we have designed direct bonded two terminal GaAsP/Si dual junction solar cell with the help of buffer layers. The current matching is improved in the lattice mis-matched solar cell by using quaternary compound AlGaInP buffer layer. The optimum efficiency of 19.80% is achieved under 1-Sun illumination using AM1.5G global spectrum.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115444645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Medical Diagnosis and Identification of Covid -19 by Intelligent IoT System and Resnet 18 Bilinear Deep Greedy Network 基于智能物联网系统和Resnet 18双线性深度贪婪网络的Covid -19医疗诊断与识别
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032861
Indrajit Das, Papiya Das, Aniruddha Roy, Papiya Debnath, Subhrapratim Nath
{"title":"Medical Diagnosis and Identification of Covid -19 by Intelligent IoT System and Resnet 18 Bilinear Deep Greedy Network","authors":"Indrajit Das, Papiya Das, Aniruddha Roy, Papiya Debnath, Subhrapratim Nath","doi":"10.1109/EDKCON56221.2022.10032861","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032861","url":null,"abstract":"An international health crisis has been caused by the widespread COVID-19 epidemic. COVID-19 patient diagnoses are made using deep learning, although this necessitates a massive radiography data collection in order to efficiently deliver an optimum result. This paper presents a novel Intelligent System with IoT sensors for covid 19 and \"Bilinear Resnet 18 Deep Greedy Network,\" which is effective with a limited amount of datasets. Despite peculiarities brought on by a small dataset, the suggested approach could successfully combat the anomalies of over fitting and under fitting. The suggested architecture ensures a successful conclusion when the trained model is correctly evaluated using the provided X-ray datasets of COVID-19 cases. The recommended model offers accuracy of 97%, which is superior to existing methodologies. Better precision, recall, and F1 score are provided; which are 98%, 96%, and 96.94% respectively, which is better than other existing methodology.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128914357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single Event Upset Mechanism in SRAM Latch and Its Circuit-Level prevention Technique SRAM锁存器中的单事件干扰机制及其电路级预防技术
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032910
M. Pandey, A. Islam
{"title":"Single Event Upset Mechanism in SRAM Latch and Its Circuit-Level prevention Technique","authors":"M. Pandey, A. Islam","doi":"10.1109/EDKCON56221.2022.10032910","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032910","url":null,"abstract":"In this paper, a 10-transistor radiation tolerant SRAM cell has been proposed using 16-nm CMOS technology. The proposed 10T SRAM cell offers higher immunity to soft error than all other compared cells. It consumes 0.68 × lower hold power than QUCCE10T SRAM cell. It exhibits 0.94 × shorter read delay compared to NS10T SRAM cell. The proposed circuit has higher RSNM than other comparison cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (QC) among all the comparison SRAM cells. In terms of $color{Blue}{text{RSNM}}$ proposed 10T is higher as compared to NS 10T, QUCCE 10T and 6T SRAM cells. However, these improvements are achieved at the cost of marginal degradation of write delay as compared to NS10T, QUCCE10T and 6T SRAM cells. Hence, the proposed 10T SRAM cell is a promising choice for future applications.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation of GaN-Based Polarization Junction Super HFET for Power Electronics Application 基于gan极化结的超级HFET电力电子应用仿真
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032828
D. Jena, Sanghamitra Das, E. Mohapatra, S. Choudhury, T. Dash
{"title":"Simulation of GaN-Based Polarization Junction Super HFET for Power Electronics Application","authors":"D. Jena, Sanghamitra Das, E. Mohapatra, S. Choudhury, T. Dash","doi":"10.1109/EDKCON56221.2022.10032828","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032828","url":null,"abstract":"Currently, polarization junctions (PJs) are the most promising candidates for power devices. PJs with wide band gap semiconductors like GaN can further enhance the performance in terms of improved breakdown voltage and less susceptible to leakage. In this work, a double-hetero GaN/AlGaN/GaN PJ is proposed to realize 2-D hole gas (2DHG) and 2-D electron gas (2DEG) at the upper and lower junction of the device. The DC, CV, and breakdown characteristics have been investigated. Moreover, the effects of bulk and interface traps on substrate leakage current and threshold voltage and breakdown voltage (BV) are also investigated. Impact ionization is observed at the drain-side boundary of the p-GaN region, and the BV is dominated by hole leakage current at the base electrode.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129968088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Mode Changing Features in the Design of Quaternary Logic Gates using CNTFET 利用CNTFET设计四元逻辑门的新模式变化特征
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032859
Anisha Paul, B. Pradhan
{"title":"Novel Mode Changing Features in the Design of Quaternary Logic Gates using CNTFET","authors":"Anisha Paul, B. Pradhan","doi":"10.1109/EDKCON56221.2022.10032859","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032859","url":null,"abstract":"This paper introduces novel mode changing features in quaternary logic gates like Inverter, NAND and NOR gates using CNTFET. Different designs of these gates are already present in the literature, but in this paper, all four types of quaternary logic gates [Standard Quaternary (SQ), Positive Quaternary (PQ), Negative Quaternary (NQ) and Intermediate Quaternary (IQ) type] are combined together in a single structure and the final output produces any one of the four types depending on some select signals. Introducing these new features into the design increases the versatility and broadens the area of application of these circuits. This paper also proposes a power-efficient quaternary minimum (QMIN) and maximum (QMAX) circuit with a lower number of CNTFETs as compared to the existing designs. The proposed circuits are simulated in HSPICE with Stanford University’s 32nm CNTFET model, and in each instance, average power values and propagation delays are duly noted.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127750416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Architecture of a fault-tolerant Memory System based on Missing Data Imputation 一种基于缺失数据输入的容错存储系统新架构
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032852
Sowvik Dey, C. Chakraborty, Sushovon Jana, M. Mahata, A. Karmakar
{"title":"A Novel Architecture of a fault-tolerant Memory System based on Missing Data Imputation","authors":"Sowvik Dey, C. Chakraborty, Sushovon Jana, M. Mahata, A. Karmakar","doi":"10.1109/EDKCON56221.2022.10032852","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032852","url":null,"abstract":"In the modern era of edge computing, each computing device is used as a resource of distributed computing elements as well as distributed storage system. Therefore, every computing device plays a crucial role in a distributed system. A huge amount of data are being collected, processed, and stored at every moment. Different kinds of AI engines are being trained by these data. The consistency of data, that is stored in distributed memories, is essential for the AI engines. The absence of data, due to memory failure, is very much effective for feature extraction. Memory failure may happen due to several causes like struck-at-fault, soft-error, etc. To get consistent data, memories should be fault-tolerant, where memory can work properly in faulty conditions. This can be done either by bypassing or by predicting the data which was stored in a faulty location. In this paper, the design of a novel architecture of memory is proposed which can predict the missing data due to memory failure.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-k SOI GaN FinFET for High Power and High Frequency Applications 高功率和高频应用的高k SOI GaN FinFET
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032945
Vandana Singh Rajawat, Bharat Choudhary, Ajay Kumar
{"title":"High-k SOI GaN FinFET for High Power and High Frequency Applications","authors":"Vandana Singh Rajawat, Bharat Choudhary, Ajay Kumar","doi":"10.1109/EDKCON56221.2022.10032945","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032945","url":null,"abstract":"This paper proposes a 3-D simulation study of high-k SOI GaN FinFET. High ON current, faster- speed, lower subthreshold swing is obtained thus suppressing the short channel effects more effectively. Extremely low OFF current is obtained due to bulk conduction in the GaN channel layer, which can be fully depleted. Various electrical parameters obtained are compared with Bulk GaN FinFET and Conventional FinFET (Si-based). Proposed FinFET is designed by using a metal gate and high-K oxide (HfO2) is used as the gate oxide layer. The proposed High-k SOI GaN FinFET has come out as a very viable option because it is known for high performance and high-speed integrated circuits; and also for high frequency and high power applications due to using high mobility GaN fin instead of silicon fin used in conventional devices.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"2871 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127446105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical Noise Analysis of Gate-on-Source Tunnel Field Effect Transistor 源上门隧场效应晶体管的电噪声分析
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) Pub Date : 2022-11-26 DOI: 10.1109/EDKCON56221.2022.10032931
S. Chander, S. K. Sinha
{"title":"Electrical Noise Analysis of Gate-on-Source Tunnel Field Effect Transistor","authors":"S. Chander, S. K. Sinha","doi":"10.1109/EDKCON56221.2022.10032931","DOIUrl":"https://doi.org/10.1109/EDKCON56221.2022.10032931","url":null,"abstract":"This work present the electrical noise analysis of a homojunction and heterojunction tunnel-field-effect-transistors (TFET) with conventional TFET and gate-on-source (GoS) structures. A detailed investigation of the proposed GoS structure with conventional structure of 20 nm gate length is performed. Based on the simulation results, it has been found that the proposed GoS using Ge as source material exhibits high on-state current of 3.78×10-5 A/μm, and low leakage current of 7.84×10-13 A/μm, and average sub-threshold slope (SSavg) of 37 mV/dec. The different figure of merits (FOMs) such as transconductance (gm), output conductance (gd), gate-source capacitance (Cgs), gate-drain capacitance (Cgd) are analysed using Synopsys TCAD. The electrical noise analysis of all four structures has been carried out at low frequency (LF) of 1 MHz and high frequency (HF) of 1 GHz. The impact of noise in proposed heterojunction GoS TFET is comparatively less than heterojunction Conventional TFET. The proposed heterojunction GoS TFET device shows good performamce in terms of on-off ratio, SS and is free from ambipolarity conduction. The heterojunction GoS can be a suitable candidate for low power applications.","PeriodicalId":296883,"journal":{"name":"2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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