Electrical Noise Analysis of Gate-on-Source Tunnel Field Effect Transistor

This work present the electrical noise analysis of a homojunction and heterojunction tunnel-field-effect-transistors (TFET) with conventional TFET and gate-on-source (GoS) structures. A detailed investigation of the proposed GoS structure with conventional structure of 20 nm gate length is performed. Based on the simulation results, it has been found that the proposed GoS using Ge as source material exhibits high on-state current of 3.78×10-5 A/μm, and low leakage current of 7.84×10-13 A/μm, and average sub-threshold slope (SSavg) of 37 mV/dec. The different figure of merits (FOMs) such as transconductance (gm), output conductance (gd), gate-source capacitance (Cgs), gate-drain capacitance (Cgd) are analysed using Synopsys TCAD. The electrical noise analysis of all four structures has been carried out at low frequency (LF) of 1 MHz and high frequency (HF) of 1 GHz. The impact of noise in proposed heterojunction GoS TFET is comparatively less than heterojunction Conventional TFET. The proposed heterojunction GoS TFET device shows good performamce in terms of on-off ratio, SS and is free from ambipolarity conduction. The heterojunction GoS can be a suitable candidate for low power applications.