Single Event Upset Mechanism in SRAM Latch and Its Circuit-Level prevention Technique

Abstract

In this paper, a 10-transistor radiation tolerant SRAM cell has been proposed using 16-nm CMOS technology. The proposed 10T SRAM cell offers higher immunity to soft error than all other compared cells. It consumes 0.68 × lower hold power than QUCCE10T SRAM cell. It exhibits 0.94 × shorter read delay compared to NS10T SRAM cell. The proposed circuit has higher RSNM than other comparison cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (QC) among all the comparison SRAM cells. In terms of $\color{Blue}{\text{RSNM}}$ proposed 10T is higher as compared to NS 10T, QUCCE 10T and 6T SRAM cells. However, these improvements are achieved at the cost of marginal degradation of write delay as compared to NS10T, QUCCE10T and 6T SRAM cells. Hence, the proposed 10T SRAM cell is a promising choice for future applications.