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Proceedings. 21st VLSI Test Symposium, 2003.最新文献

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Testable design and testing of micro-electro-fluidic arrays 微电-流控阵列的可测试设计与测试
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197681
H. Kerkhoff, M. Acar
{"title":"Testable design and testing of micro-electro-fluidic arrays","authors":"H. Kerkhoff, M. Acar","doi":"10.1109/VTEST.2003.1197681","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197681","url":null,"abstract":"The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multidomain fault modeling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. The fault simulations also reveal important parameters of multi-domain test-stimuli, e.g. fluid velocity, for detecting both electrical and fluidic defects.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Automatic configuration generation for FPGA interconnect testing FPGA互连测试的自动配置生成
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197644
M. Tahoori, S. Mitra
{"title":"Automatic configuration generation for FPGA interconnect testing","authors":"M. Tahoori, S. Mitra","doi":"10.1109/VTEST.2003.1197644","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197644","url":null,"abstract":"We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Power constrained test scheduling with dynamically varied TAM 动态变化TAM的功率约束测试调度
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197663
Dan Zhao, S. Upadhyaya
{"title":"Power constrained test scheduling with dynamically varied TAM","authors":"Dan Zhao, S. Upadhyaya","doi":"10.1109/VTEST.2003.1197663","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197663","url":null,"abstract":"In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123768210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
An analog checker with dynamically adjustable error threshold for fully differential circuits 具有动态可调误差阈值的模拟检查器，用于全差分电路
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197653
H. Stratigopoulos, Y. Makris
{"title":"An analog checker with dynamically adjustable error threshold for fully differential circuits","authors":"H. Stratigopoulos, Y. Makris","doi":"10.1109/VTEST.2003.1197653","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197653","url":null,"abstract":"We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate concurrent error detection in analog circuits. Dynamic error threshold adjustment is achieved by regulating the bias point of the output stage inverters of the checker, which provide a digital indication of potential errors in the circuit under test. We discuss the theoretical foundation and we present simulations that validate the underlying principle of the design. As compared to previous solutions, the proposed checker reduces the incurred overhead, while significantly enhancing the quality of concurrent error detection.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114865290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Eliminating non-determinism during test of high-speed source synchronous differential buses 消除高速源同步差动母线试验中的不确定性
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197642
K. Mohanram, N. Touba
{"title":"Eliminating non-determinism during test of high-speed source synchronous differential buses","authors":"K. Mohanram, N. Touba","doi":"10.1109/VTEST.2003.1197642","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197642","url":null,"abstract":"The at-speed functional testing of deep sub-micron devices equipped with high-speed I/O ports and the asynchronous nature of such I/O transactions poses significant challenges. In this paper, the problem of nondeterminism in the output response of the device-under-test (DUT) is described. This can arise due to limited automated test equipment (ATE) edge placement accuracy(EPA) in the source synchronous clock of the stimulus stream to the high-speed I/O port from the tester. A simple yet effective solution that uses a trigger signal to initiate a deterministic transfer of test inputs into the core clock domain of the DUT from the high-speed I/O port is presented. The solution allows the application of at-speed functional patterns to the DUT while incurring a very small hardware overhead and trivial increase in test application time. An analysis of the probability of non-determinism as a function of clock speed and EPA is presented. It shows that as the frequency of operation of high-speed I/Os continues to rise, non-determinism will become a significant problem that can result in an unacceptable yield loss.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Built-in reseeding for serial BIST 内置重新播种串行BIST
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197634
Ahmad A. Al-Yamani, E. McCluskey
{"title":"Built-in reseeding for serial BIST","authors":"Ahmad A. Al-Yamani, E. McCluskey","doi":"10.1109/VTEST.2003.1197634","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197634","url":null,"abstract":"Reseeding is used to improve fault coverage in BIST pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The seeds are encoded in hardware. The seeds we use are deterministic so 100% fault coverage can be achieved. Our technique causes no performance overhead and does not change the original circuit under test. Also, the technique we present is applicable for transition faults as well as single-stuck-at faults. Built-in reseeding is based on expanding every seed to as many ATPG patterns as possible. This is different from many existing reseeding techniques that expand every seed into a single ATPG pattern. This paper presents the built-in reseeding algorithm together with a hardware synthesis algorithm and implementation.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Analyzing crosstalk in the presence of weak bridge defects 存在弱桥缺陷时串扰分析
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197679
Shahdad Irajpour, Shahin Nazarian, Lei Wang, S. Gupta, M. Breuer
{"title":"Analyzing crosstalk in the presence of weak bridge defects","authors":"Shahdad Irajpour, Shahin Nazarian, Lei Wang, S. Gupta, M. Breuer","doi":"10.1109/VTEST.2003.1197679","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197679","url":null,"abstract":"An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered. Scenarios have been identified where a combination of a bridge at one site and a crosstalk at a separate site in its transitive fanout (or vice versa) can cause slowdown/speed-up whose magnitude significantly exceeds the sum of the slow-down/speed-up, caused by each effect in isolation. It has also been identified that a test vector generated for crosstalk may in fact be invalidated due to the presence of a weak bridge at the crosstalk site. The properties discovered, provide the motivation for a more analytical study that will eventually lead to the proposed framework for test development.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133493967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Effectiveness of I-V testing in comparison to IDDq tests [IC testing] 与IDDq测试相比，I-V测试的有效性[IC测试]
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197632
T. Vogels
{"title":"Effectiveness of I-V testing in comparison to IDDq tests [IC testing]","authors":"T. Vogels","doi":"10.1109/VTEST.2003.1197632","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197632","url":null,"abstract":"This paper contrasts the novel I-V test criteria with traditional and recent IDDq test methods and compares their test effectiveness. It shows how I-V tests and IDDq tests fare in discriminating between \"good\" and \"bad\" dies and how test limits can be set empirically, especially for I-V testing. All results are based on data from an (internal) IBM experiment that was based on a large ASIC manufactured in a 0.18 /spl mu/m-L/sub eff/ technology.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design for self-checking and self-timed datapath 设计自检和自定时数据路径
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197683
Jing-ling Yang, O. Choy, C. Chan, K. Pun
{"title":"Design for self-checking and self-timed datapath","authors":"Jing-ling Yang, O. Choy, C. Chan, K. Pun","doi":"10.1109/VTEST.2003.1197683","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197683","url":null,"abstract":"This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124780458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
DSP-based statistical self test of on-chip converters 基于dsp的片上转换器的统计自检
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197637
Hak-soo Yu, Sungbae Hwang, J. Abraham
{"title":"DSP-based statistical self test of on-chip converters","authors":"Hak-soo Yu, Sungbae Hwang, J. Abraham","doi":"10.1109/VTEST.2003.1197637","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197637","url":null,"abstract":"We propose a DSP-based statistical self test approach for testing on-chip data converters. Analog to digital converters (ADCs) and digital to analog converters (DACs) can be tested in a loop-back mode, providing a go/no-go result; however such tests focus on catastrophic fault coverage. We develop a technique for testing converters in loop-back mode which is simple, but has good parametric as well as catastrophic fault coverage. We use the on-chip digital signal processing unit to generate test stimuli. The analysis of the results is done through the use of software on the DSP unit which is capable of monitoring primary inputs, outputs and/or internal nodes. Characterization of actual /spl Delta//spl Sigma/ converters was performed to show the feasibility of the proposed method.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116050813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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