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Proceedings. 21st VLSI Test Symposium, 2003.最新文献

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High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost 高覆盖模拟晶圆探针测试设计和集成封装测试协同优化，以最大限度地降低整体测试成本
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197638
S. Bhattacharya, A. Chatterjee
{"title":"High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost","authors":"S. Bhattacharya, A. Chatterjee","doi":"10.1109/VTEST.2003.1197638","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197638","url":null,"abstract":"It is well known that wafer probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much as the testing process into wafer-probe lest as possible while limiting the scope of assembled package test. However, the signal drive and response observation capabilities during wafer probe lest are limited in comparison to assembled package test. In this paper, it is shown that by marginally increasing the capabilities of wafer probe lest equipment to include low-speed transient signals, significant numbers of bad ICs can be detected early during wafer probe lest. The optimal test stimulus is determined by co-optimizing the wafer-probe and assembled package test waveforms. Overall, test costs, including the cost of packaging bad ICs are minimized.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs 复杂集成电路中频率相关缺陷异常值筛选方法的有效性比较
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197631
B. Benware, R. Madge, Cam Lu, W. R. Daasch
{"title":"Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs","authors":"B. Benware, R. Madge, Cam Lu, W. R. Daasch","doi":"10.1109/VTEST.2003.1197631","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197631","url":null,"abstract":"In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a series of ASIC products and it has been used to compare the effectiveness of full vector set transition delay fault tests with reduced vector sets, minVDD, customer functional tests and customers system fails. Results show that fault models do not predict the defect coverage well and cost effective screening of frequency outliers and minVDD outliers is possible and is critical in improving customer quality.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126246977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Path-delay fault simulation for circuits with large numbers of paths for very large test sets 针对非常大的测试集，对具有大量路径的电路进行路径延迟故障仿真
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197650
Nabil M. Abdulrazzaq, S. Gupta
{"title":"Path-delay fault simulation for circuits with large numbers of paths for very large test sets","authors":"Nabil M. Abdulrazzaq, S. Gupta","doi":"10.1109/VTEST.2003.1197650","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197650","url":null,"abstract":"We propose an exact non-enumerative path-delay fault simulation technique for combinational circuits using very large test sets. We focus on combinational circuits that contain very large numbers of path delay faults, for example, c6288 that has about 2/spl times/10/sup 20/ possible path-delay faults. Enumerative fault simulators simply cannot handle such circuits. Existing non-enumerative fault simulators work for small test sets only. The proposed method uses the mathematical principle of inclusion and exclusion and handles the large number of tests using a novel encoding technique.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Generating complete and optimal march tests for linked faults in memories 为存储器中的关联故障生成完整和最佳的行军测试
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197659
Sultan M. Al-Harbi, S. Gupta
{"title":"Generating complete and optimal march tests for linked faults in memories","authors":"Sultan M. Al-Harbi, S. Gupta","doi":"10.1109/VTEST.2003.1197659","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197659","url":null,"abstract":"We show that no published march test detects all march-test detectable instances of linked faults in memories. We present necessary and sufficient conditions for detection of single cell linked faults. We identify the set of faults that are undetectable by march tests. We also present sets of faults that dominate all march-test detectable instances of linked multiple cell faults along with the necessary and sufficient conditions for their detection. Using a test generator that takes these conditions as input, we generate the first march tests that detect all march-test detectable linked faults. By considering the subsets of linked faults targeted by the well-known March A and March B tests, we also prove that these well-known tests are optimal for the corresponding sets of target faults.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128821456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Testing SoC interconnects for signal integrity using boundary scan 测试SoC互连的信号完整性使用边界扫描
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197647
M. Tehranipour, N. Ahmed, M. Nourani
{"title":"Testing SoC interconnects for signal integrity using boundary scan","authors":"M. Tehranipour, N. Ahmed, M. Nourani","doi":"10.1109/VTEST.2003.1197647","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197647","url":null,"abstract":"As the technology is shrinking toward 50 nm and the working frequency is going into the multi Gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we extend the conventional boundary scan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant. We also propose a simple yet efficient compression scheme that can be employed by an ATE to minimize the scan-in delivery time.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121898402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Keynote Address 主题演讲
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 1900-01-01 DOI: 10.1109/VTEST.2003.1197623
J. Fields
{"title":"Keynote Address","authors":"J. Fields","doi":"10.1109/VTEST.2003.1197623","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197623","url":null,"abstract":"","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114996440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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