High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost

Abstract

It is well known that wafer probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much as the testing process into wafer-probe lest as possible while limiting the scope of assembled package test. However, the signal drive and response observation capabilities during wafer probe lest are limited in comparison to assembled package test. In this paper, it is shown that by marginally increasing the capabilities of wafer probe lest equipment to include low-speed transient signals, significant numbers of bad ICs can be detected early during wafer probe lest. The optimal test stimulus is determined by co-optimizing the wafer-probe and assembled package test waveforms. Overall, test costs, including the cost of packaging bad ICs are minimized.