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Proceedings. 21st VLSI Test Symposium, 2003.最新文献

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Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression 通过统一的测试模式压缩和压缩来减少测试体积和时间的解压硬件确定
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197641
I. Bayraktaroglu, A. Orailoglu
{"title":"Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression","authors":"I. Bayraktaroglu, A. Orailoglu","doi":"10.1109/VTEST.2003.1197641","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197641","url":null,"abstract":"A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductions are delivered through the scheme we propose while a highly cost effective hardware implementation is retained.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127610936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
A test interface for built-in test of non-isolated scanned cores 一个测试接口，用于内置非隔离扫描核的测试
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197677
I. Pomeranz, S. Reddy, Y. Zorian
{"title":"A test interface for built-in test of non-isolated scanned cores","authors":"I. Pomeranz, S. Reddy, Y. Zorian","doi":"10.1109/VTEST.2003.1197677","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197677","url":null,"abstract":"We consider the problem of built-in test pattern generation for non-isolated scanned cores. When two such cores are interconnected, a block of combinational logic that spans both cores may be created. Our goal is to provide a solution for built-in testing of logic that spans multiple cores. Starting from a given test-pattern generator (TPG), we propose a design-for-testability approach to improve the fault coverage achieved by the TPG. This approach is based on designing the interfaces between pairs of cores such that they support the testing of both cores. The proposed approach does not require any modifications to the cores themselves. In a vast majority of the benchmark circuits considered, the proposed approach results in 100% fault coverage.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SOC test scheduling using simulated annealing 基于模拟退火的SOC测试调度
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197670
Wei Zou, S. Reddy, I. Pomeranz, Yu Huang
{"title":"SOC test scheduling using simulated annealing","authors":"Wei Zou, S. Reddy, I. Pomeranz, Yu Huang","doi":"10.1109/VTEST.2003.1197670","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197670","url":null,"abstract":"We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"13 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124134525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
Detecting intra-word faults in word-oriented memories 面向词记忆的词内错误检测
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197657
S. Hamdioui, A. V. Goor, M. Rodgers
{"title":"Detecting intra-word faults in word-oriented memories","authors":"S. Hamdioui, A. V. Goor, M. Rodgers","doi":"10.1109/VTEST.2003.1197657","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197657","url":null,"abstract":"This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log/sub 2/B]) * n/B test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 * n/B when the intra-word faults are restricted to physical adjacent cells within a word.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126388883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
1149.4 based on-line quiescent state monitoring technique [analog DFT] 1149.4基于在线静态状态监测技术[模拟DFT]
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197651
C. Su, Chih-hu Wang, Wei-Juo Wang, I. Tseng
{"title":"1149.4 based on-line quiescent state monitoring technique [analog DFT]","authors":"C. Su, Chih-hu Wang, Wei-Juo Wang, I. Tseng","doi":"10.1109/VTEST.2003.1197651","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197651","url":null,"abstract":"On-line quiescent state monitoring is achieved by utilizing dual comparators compatible with the IEEE 1149.4 standard analog DFT. Statistical analysis is used to minimize the impacts of dynamic signals and noise carried in the signal line. The experimental results confirm the mathematical analysis and assure the test methodology.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Use of multiple I/sub DDQ/ test metrics for outlier identification 使用多个I/sub DDQ/测试指标进行异常值识别
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197630
S. Sabade, D. Walker
{"title":"Use of multiple I/sub DDQ/ test metrics for outlier identification","authors":"S. Sabade, D. Walker","doi":"10.1109/VTEST.2003.1197630","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197630","url":null,"abstract":"With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for I/sub DDQ/ test due to increased spread in the distribution. In this paper, the concept of current ratio is extended to exploit wafer-level spatial correlation. Two metrics - current ratio and neighbor current ratio - are combined to screen outliers at the wafer level. We demonstrate that a single metric alone cannot screen all outliers, however, their combination can be used for effectively screening outlier chips. Analyses based on industrial test data are presented.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134440266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Test resource partitioning and optimization for SOC designs 测试资源划分和优化SOC设计
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197669
E. Larsson, H. Fujiwara
{"title":"Test resource partitioning and optimization for SOC designs","authors":"E. Larsson, H. Fujiwara","doi":"10.1109/VTEST.2003.1197669","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197669","url":null,"abstract":"We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133803636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Improving diagnostic resolution of delay faults using path delay fault model 利用路径延迟故障模型提高延迟故障的诊断分辨率
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197673
A. Majhi, G. Gronthoud, C. Hora, M. Lousberg, Pop Valer, S. Eichenberger
{"title":"Improving diagnostic resolution of delay faults using path delay fault model","authors":"A. Majhi, G. Gronthoud, C. Hora, M. Lousberg, Pop Valer, S. Eichenberger","doi":"10.1109/VTEST.2003.1197673","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197673","url":null,"abstract":"The known methods of transition fault diagnosis usually suffer from the drawback of many candidates. The method presented in this paper aims at reducing the number of suspects. The transition fault patterns were generated by Philips in-house ATPG tool and applied on the tester. The fail information from tester was subjected to fault diagnosis resulting in a small list of faulty candidates. We then injected the delay faults into the golden netlist of the test chip and confirmed through simulation whether or not their behavior matched with the tester results. Upon successful matching, we proceeded with the selection of few testable paths through the suspect faulty node and created corresponding path delay patterns using the path delay ATPG (a prototype at the University of Bremen, developed in cooperation with Philips Semiconductors GmbH, Hamburg). Finally, we verified those path delay patterns on the tester to increase the confidence level of the diagnosis method The experimental results show the effectiveness of our novel approach for improving diagnostic resolution.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Test and diagnosis of word-oriented multiport memories 面向词的多端口记忆的测试与诊断
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197658
Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
{"title":"Test and diagnosis of word-oriented multiport memories","authors":"Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu","doi":"10.1109/VTEST.2003.1197658","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197658","url":null,"abstract":"Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observability and controllability that effectively reduces the test time. Our key idea is that a sequence of March operations for any memory cell can be folded and executed within a single access cycle. We have also developed an efficient test algorithm for port-specific faults as well as traditional cell faults. The port-specific faults include the stuck-open, address decoder, and inter-port faults, for both bit-oriented and word-oriented RAMs. Experimental results for our folding scheme show that the test time reduction is about 28% for a commercial 8 KB embedded SRAM. An efficient diagnostic algorithm is also proposed for the port-specific faults and traditional cell faults.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Energy-efficient logic BIST based on state correlation analysis 基于状态相关分析的节能逻辑BIST
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197662
Xiaoding Chen, M. Hsiao
{"title":"Energy-efficient logic BIST based on state correlation analysis","authors":"Xiaoding Chen, M. Hsiao","doi":"10.1109/VTEST.2003.1197662","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197662","url":null,"abstract":"We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also allows us to omit some flip-flops in the scan chain. By leaving flip-flops that need less control out of the scan chain, we can reduce transitions on those flip-flops, thereby reducing the overall power and energy. The omission of flip-flops are done in a way that the fault coverage is unaffected. Furthermore, reordering of the flip-flops in the scan chain allows the generated patterns to be more compatible with the state sequence necessary for exciting the random-pattern-resistant faults. Our experiments show that the same or higher fault coverage can be achieved with less energy (and average power) - average power of 48.5% is reduced, with the maximum reduction of 73%.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114478678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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