DSP-based statistical self test of on-chip converters

We propose a DSP-based statistical self test approach for testing on-chip data converters. Analog to digital converters (ADCs) and digital to analog converters (DACs) can be tested in a loop-back mode, providing a go/no-go result; however such tests focus on catastrophic fault coverage. We develop a technique for testing converters in loop-back mode which is simple, but has good parametric as well as catastrophic fault coverage. We use the on-chip digital signal processing unit to generate test stimuli. The analysis of the results is done through the use of software on the DSP unit which is capable of monitoring primary inputs, outputs and/or internal nodes. Characterization of actual /spl Delta//spl Sigma/ converters was performed to show the feasibility of the proposed method.