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Proceedings. 21st VLSI Test Symposium, 2003.最新文献

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An embedded autonomous scan-based results analyzer (EARA) for SoC cores 用于SoC核心的嵌入式自主扫描结果分析仪(EARA)
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197666
M. Nahvi, A. Ivanov
{"title":"An embedded autonomous scan-based results analyzer (EARA) for SoC cores","authors":"M. Nahvi, A. Ivanov","doi":"10.1109/VTEST.2003.1197666","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197666","url":null,"abstract":"Relying solely upon external ATE resources for scan test in complex SoC designs is increasingly difficult. In this work, we develop the concept and implementation of an embedded autonomous results analyzer (EARA) to be used in our modified dedicated autonomous scan-based testing (DAST) methodology. DAST introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication; and b) test data control and observation. Consequently, test data control/observation functions are transferred to embedded blocks. In this work, we extend DAST to include the sending of expected test results along with the test stimulus to enable on-chip comparison. We present implementation results of EARA when applied to a number of SoC benchmarks.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Test generation for maximizing ground bounce considering circuit delay 考虑电路延迟最大化地反弹的测试生成
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197646
Yi-Shing Chang, S. Gupta, M. Breuer
{"title":"Test generation for maximizing ground bounce considering circuit delay","authors":"Yi-Shing Chang, S. Gupta, M. Breuer","doi":"10.1109/VTEST.2003.1197646","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197646","url":null,"abstract":"In this paper, we focus on the aspect of ground bounce due to the combination of current produced by gates (signals) switching and the flow of this current through pin electronics. We present a branch-and-bound test generation procedure to obtain high quality 2-vector tests that produce a large amount of ground bounce. We present a framework that accurately captures the relationship between a test and the associated relative size of the maximum amount of ground bounce while taking into account gate delay. Experimental results show that our search procedure can efficiently and effectively find a test that produces the maximum value of ground bounce. We also discuss a binary search based approach that allows our search to cover a larger portion of the search space and find a good test in a reduced amount of CPU time.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123160476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Threshold voltage mismatch (/spl Delta/V/sub T/) fault modeling 阈值电压失配(/spl Delta/V/sub T/)故障建模
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197645
J. P. D. Gyvez, R. Rodríguez-Montañés
{"title":"Threshold voltage mismatch (/spl Delta/V/sub T/) fault modeling","authors":"J. P. D. Gyvez, R. Rodríguez-Montañés","doi":"10.1109/VTEST.2003.1197645","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197645","url":null,"abstract":"A reduced intrinsic threshold voltage (V/sub T/) in addition to its variability has a direct impact on circuit design. Worst-case design styles assume that all transistors use the same worst-case V/sub T/ whose average and standard deviation come from inter-die statistical variations. However, intra-die differences, such as random local V/sub T/ variations are not considered and may pose a serious problem for designs based on low-voltage low-power premises, e.g. clock skews, excessive leakage current, out of spec critical-path delays, etc. This paper formulates a fault model based on threshold voltage mismatch and analyzes its impact on circuit design. Simulation and experimental results support the fault model.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132332042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A reconfigurable shared scan-in architecture 一个可重构的共享扫描架构
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197627
S. Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, R. Kapur, T. Williams
{"title":"A reconfigurable shared scan-in architecture","authors":"S. Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, R. Kapur, T. Williams","doi":"10.1109/VTEST.2003.1197627","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197627","url":null,"abstract":"In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132785785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 97
Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation 诊断试验生成过程中诊断故障模拟与等效性识别并行执行
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197674
X. Yu, M. E. Amyeen, S. Venkataraman, Ruifeng Guo, I. Pomeranz
{"title":"Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation","authors":"X. Yu, M. E. Amyeen, S. Venkataraman, Ruifeng Guo, I. Pomeranz","doi":"10.1109/VTEST.2003.1197674","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197674","url":null,"abstract":"Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
BIST-aided scan test - a new method for test cost reduction bist辅助扫描测试——降低测试成本的新方法
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197675
Takahisa Hiraide, K. Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, H. Yamanaka, T. Mochiyama
{"title":"BIST-aided scan test - a new method for test cost reduction","authors":"Takahisa Hiraide, K. Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, H. Yamanaka, T. Mochiyama","doi":"10.1109/VTEST.2003.1197675","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197675","url":null,"abstract":"It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128867346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Application of Saluja-Karpovsky compactors to test responses with many unknowns Saluja-Karpovsky压实机在多未知数响应测试中的应用
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197640
J. Patel, S. Lumetta, S. Reddy
{"title":"Application of Saluja-Karpovsky compactors to test responses with many unknowns","authors":"J. Patel, S. Lumetta, S. Reddy","doi":"10.1109/VTEST.2003.1197640","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197640","url":null,"abstract":"This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes. The technique, called i-Compact, uses Saluja-Karpovsky Space Compactors, but permits detection and location of errors in the presence of unknown logic (X) values with help from the ATE. The advantages of i-Compact are: 1. Small number of output pins front the compactors for a required error detection capability; 2. Small tester memory for storing expected responses; 3. Flexibility of choosing several different combinations of number of X values and number of bit errors for error detection without altering the hardware compactor; 4. Same hardware capable of identifying the line that produced an error in presence of unknowns; 5. Use of non-proprietary codes found in the literature of 1950s; and 6. Independent of the circuit and the test generator.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128455078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 111
Design and optimization of multi-level TAM architectures for hierarchical SOCs 面向分层soc的多级TAM体系结构设计与优化
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197667
V. Iyengar, K. Chakrabarty, M. Krasniewski, Gopind N. Kumar
{"title":"Design and optimization of multi-level TAM architectures for hierarchical SOCs","authors":"V. Iyengar, K. Chakrabarty, M. Krasniewski, Gopind N. Kumar","doi":"10.1109/VTEST.2003.1197667","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197667","url":null,"abstract":"Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC'02 SOC test benchmarks.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127540746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Diagnosis of delay defects using statistical timing models 用统计时序模型诊断时延缺陷
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197672
Angela Krstic, Li-C. Wang, K. Cheng, J. Liou
{"title":"Diagnosis of delay defects using statistical timing models","authors":"Angela Krstic, Li-C. Wang, K. Cheng, J. Liou","doi":"10.1109/VTEST.2003.1197672","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197672","url":null,"abstract":"In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timing information based upon single defect assumption. We evaluate its performance and its applicability to single as well as multiple defect scenarios via statistical defect injection and simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concept in statistical delay defect diagnosis, and discuss experimental results using benchmark circuits.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Test consideration for nanometer scale CMOS circuits 纳米级CMOS电路的测试考虑
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197668
K. Roy, T. M. Mak, K. Cheng
{"title":"Test consideration for nanometer scale CMOS circuits","authors":"K. Roy, T. M. Mak, K. Cheng","doi":"10.1109/VTEST.2003.1197668","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197668","url":null,"abstract":"The ITRS (international technology roadmap for semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. Such scaling will result in an exponential increase in leakage current and large variability in threshold voltage both within and across dies. Device counts will increase from about 0.2 B/chip today to approximately 10 B/chip in a decade. This 50/spl times/ increase in device count will increase not only the active power dissipation, but also the standby or the quiescent power. Hence, designers are required to use innovative aggressive power management strategies to meet the power constraints. The exponential increase in leakage, the device parameter variations, and aggressive power management techniques are expected to severely impact the way integrated circuits are tested today. This paper explores test considerations for the scaled CMOS circuits in the nanometer regime.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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