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Proceedings. 21st VLSI Test Symposium, 2003.最新文献

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Efficient implication-based untestable bridge fault identifier 高效的基于隐式的不可测桥梁故障识别器
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197680
M. Syal, M. Hsiao, K. B. Doreswamy, S. Chakravarty
{"title":"Efficient implication-based untestable bridge fault identifier","authors":"M. Syal, M. Hsiao, K. B. Doreswamy, S. Chakravarty","doi":"10.1109/VTEST.2003.1197680","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197680","url":null,"abstract":"This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation is first performed, as a preprocessing step, to identify nets which are uncontrollable to a specific logic value. Then, an implication-based analysis is carried out for each fault to determine if a particular fault is testable or not. We also use information about the untestable stuck-at faults to filter out some bridges early in the analysis process. The application of our technique to ISCAS '89 sequential benchmark circuits and a few industrial circuits showed that a large number of untestable bridges could be identified at a low cost, both in terms of memory and execution time.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132664858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Layered approach to designing system test interfaces 分层方法设计系统测试接口
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197671
Man Wah Chiang, Z. Zilic
{"title":"Layered approach to designing system test interfaces","authors":"Man Wah Chiang, Z. Zilic","doi":"10.1109/VTEST.2003.1197671","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197671","url":null,"abstract":"The layered system design approach has shown its strength in the design of the network and other complex systems. In this paper, we apply this approach to the design of system testing interfaces. The system is partitioned into layers to maximize reuse, and ease the development. In this paper, we demonstrate this methodology by designing a low-overhead testing interface and circuitry for the Infiniband Architecture (IBA).","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture 基于Illinois扫描架构的每门最长路径测试数据压缩和测试时间缩短
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197628
Manish Sharma, J. Patel, J. Rearick
{"title":"Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture","authors":"Manish Sharma, J. Patel, J. Rearick","doi":"10.1109/VTEST.2003.1197628","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197628","url":null,"abstract":"Localized delay defects, like resistive shorts, resistive opens, etc., can be effectively detected by testing the longest testable path through each wire (or gate) in the circuit. Such a delay test set is referred to as a longest-path-per-wire test set. In this paper we study test data volume and test application time reduction techniques for such tests based on the Illinois scan architecture. We present a novel ATPG flow to quickly determine longest-path-per-wire test sets under constraints imposed by the Illinois scan architecture. Results of experiments on ISCAS sequential circuits are presented. On an average we achieve a test data volume reduction of 2.79X and number of test cycles reduction of 3.28X for robust path delay, tests (as compared to the case without Illinois scan). The corresponding numbers for non-robust tests are 3.58X and 4.24X.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114336182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Transition test generation using replicate-and-reduce transform for scan-based designs 对基于扫描的设计使用复制-缩减转换生成转换测试
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197629
M. Abadir, Juhong Zhu
{"title":"Transition test generation using replicate-and-reduce transform for scan-based designs","authors":"M. Abadir, Juhong Zhu","doi":"10.1109/VTEST.2003.1197629","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197629","url":null,"abstract":"In this paper, we presented a new transition ATPG methodology flow for scan-based design using broad-side test format. A replicate and reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicated iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126402772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A circuit level fault model for resistive opens and bridges 电阻开路和电桥的电路级故障模型
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197678
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. Walker
{"title":"A circuit level fault model for resistive opens and bridges","authors":"Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. Walker","doi":"10.1109/VTEST.2003.1197678","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197678","url":null,"abstract":"Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Deterministic test vector decompression in software using linear operations [SOC testing] 基于线性操作的软件确定性测试向量解压缩[SOC测试]
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197655
K. J. Balakrishnan, N. Touba
{"title":"Deterministic test vector decompression in software using linear operations [SOC testing]","authors":"K. J. Balakrishnan, N. Touba","doi":"10.1109/VTEST.2003.1197655","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197655","url":null,"abstract":"A new software-based test vector compression technique is proposed for using an embedded processor to test the other components of a system-on-a-chip (SOC). The tester transfers compressed test data to the processor's on-chip memory, and the processor executes a small program which decompresses the data and applies it to the scan chains of each core-under-test. The proposed decompression procedure uses word-based linear operations to expand the compressed test data into the corresponding deterministic test vectors. It has a number of nice features that overcome the drawbacks of software-based linear feedback shift register (LFSR) reseeding. The storage requirements for the proposed approach depend only on the total number of specified bits in the test set. There are no restrictions on static compaction or the test generation procedure as a whole. The decompression program can be easily reused for applying different test sets. Experimental results demonstrate that the proposed approach compares very favorably with all previously published results for software-based test vector decompression.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115139968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Design for consecutive transparency of cores in system-on-a-chip 片上系统中连续透明核的设计
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197665
T. Yoneda, H. Fujiwara
{"title":"Design for consecutive transparency of cores in system-on-a-chip","authors":"T. Yoneda, H. Fujiwara","doi":"10.1109/VTEST.2003.1197665","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197665","url":null,"abstract":"This paper presents a design-for-consecutive-transparency method that makes a soft core (RTL description) consecutively transparent using integer linear programming. Consecutive transparency of a core guarantees consecutive propagation of arbitrary test/response sequences from the core inputs to the core outputs with some latency. Therefore, it is possible to apply/observe arbitrary test/response sequences to/from an embedded core consecutively at the speed of the system clock by using interconnects and consecutively transparent cores in an SoC. Experimental results show that the proposed method introduces a lower area overhead compared to the bypass method that adds direct paths from PIs to POs with multiplexers.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"613 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123076048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ultra low cost analog BIST using spectral analysis 超低成本模拟BIST使用频谱分析
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197636
M. Negreiros, L. Carro, A. Susin
{"title":"Ultra low cost analog BIST using spectral analysis","authors":"M. Negreiros, L. Carro, A. Susin","doi":"10.1109/VTEST.2003.1197636","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197636","url":null,"abstract":"In this work, a low cost method to implement an analog BIST scheme for the system on chip environment is presented. The method is based on spectral analysis and it is entirely digital. A simple and low cost 1-bit digitizer is used to capture analog information without the need for an AD converter or oversampling techniques. It also allows partitioning of the analog circuit for test thanks to the low analog area overhead of the digitizer. The mathematical framework and a test example are presented, with practical results illustrating limitations and advantages of the proposed technique.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Built-in TPG with designed phaseshifts 内置TPG与设计相移
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197676
D. Kagaris
{"title":"Built-in TPG with designed phaseshifts","authors":"D. Kagaris","doi":"10.1109/VTEST.2003.1197676","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197676","url":null,"abstract":"In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123887129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The impact of NoC reuse on the testing of core-based systems NoC重用对基于核心的系统测试的影响
Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI: 10.1109/VTEST.2003.1197643
É. Cota, M. Kreutz, C. Zeferino, L. Carro, M. Lubaszewski, A. Susin
{"title":"The impact of NoC reuse on the testing of core-based systems","authors":"É. Cota, M. Kreutz, C. Zeferino, L. Carro, M. Lubaszewski, A. Susin","doi":"10.1109/VTEST.2003.1197643","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197643","url":null,"abstract":"The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
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