NoC重用对基于核心的系统测试的影响

Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI:10.1109/VTEST.2003.1197643

É. Cota, M. Kreutz, C. Zeferino, L. Carro, M. Lubaszewski, A. Susin

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引用次数: 92

摘要

作者建议重用片上网络来测试使用该平台的基于核心的系统。从最小化测试时间的角度出发，提出并讨论了两种重用的可能性。提出了一种利用网络特性减少测试时间的算法。实验结果表明，该方法可以充分利用网络的并行化能力，减少系统测试时间，同时有效地减小了网络的面积和引脚开销。

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The impact of NoC reuse on the testing of core-based systems

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

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Proceedings. 21st VLSI Test Symposium, 2003.

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