内置TPG与设计相移

D. Kagaris
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引用次数: 12

摘要

在本文中,我们提出了内置的测试模式生成(TPG)机制,该机制可以在由其连续阶段产生的位序列上强制执行规定的精确相移集或信道分离,同时仍然需要低硬件开销。这种机制用于控制二维TPG体系结构中对伪随机和伪穷举TPG有问题的相关性和/或线性依赖性的数量。硬件开销的减少是通过一种新技术实现的,该技术将原始TPG机制的逻辑与所需移相器网络的逻辑相结合,以产生改进的紧凑结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Built-in TPG with designed phaseshifts
In this paper, we present built-in test pattern generation (TPG) mechanisms that can enforce a prescribed exact set of phaseshifts, or channel separations, on the bit sequences produced by their successive stages, while still requiring low hardware overhead. Such mechanisms are used in controlling the amount of correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive TPG in a two-dimensional TPG architecture. The reduction in hardware overhead is achieved by a new technique that merges the logic of the original TPG mechanism with that of the required phase shifter network in order to yield an improved compact structure.
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