Test generation for maximizing ground bounce considering circuit delay

Abstract

In this paper, we focus on the aspect of ground bounce due to the combination of current produced by gates (signals) switching and the flow of this current through pin electronics. We present a branch-and-bound test generation procedure to obtain high quality 2-vector tests that produce a large amount of ground bounce. We present a framework that accurately captures the relationship between a test and the associated relative size of the maximum amount of ground bounce while taking into account gate delay. Experimental results show that our search procedure can efficiently and effectively find a test that produces the maximum value of ground bounce. We also discuss a binary search based approach that allows our search to cover a larger portion of the search space and find a good test in a reduced amount of CPU time.